board/gateworks/gw_ventana/gw_ventana.c

   1 /*
   2  * Copyright (C) 2013 Gateworks Corporation
   3  *
   4  * Author: Tim Harvey <tharvey@gateworks.com>
   5  *
   6  * SPDX-License-Identifier: GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/crm_regs.h>
  12 #include <asm/arch/iomux.h>
  13 #include <asm/arch/mx6-pins.h>
  14 #include <asm/arch/mxc_hdmi.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/gpio.h>
  17 #include <asm/imx-common/boot_mode.h>
  18 #include <asm/imx-common/sata.h>
  19 #include <asm/imx-common/spi.h>
  20 #include <asm/imx-common/video.h>
  21 #include <asm/io.h>
  22 #include <dm.h>
  23 #include <dm/platform_data/serial_mxc.h>
  24 #include <hwconfig.h>
  25 #include <i2c.h>
  26 #include <fdt_support.h>
  27 #include <fsl_esdhc.h>
  28 #include <jffs2/load_kernel.h>
  29 #include <linux/ctype.h>
  30 #include <miiphy.h>
  31 #include <mtd_node.h>
  32 #include <netdev.h>
  33 #include <pci.h>
  34 #include <power/pmic.h>
  35 #include <power/ltc3676_pmic.h>
  36 #include <power/pfuze100_pmic.h>
  37 #include <fdt_support.h>
  38 #include <jffs2/load_kernel.h>
  39 #include <spi_flash.h>
  40
  41 #include "gsc.h"
  42 #include "common.h"
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46
  47 /*
  48  * EEPROM board info struct populated by read_eeprom so that we only have to
  49  * read it once.
  50  */
  51 struct ventana_board_info ventana_info;
  52
  53 static int board_type;
  54
  55 /* MMC */
  56 static iomux_v3_cfg_t const usdhc3_pads[] = {
  57         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  58         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  59         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  60         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  61         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  62         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  63         /* CD */
  64         IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00  | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
  65 };
  66
  67 /* ENET */
  68 static iomux_v3_cfg_t const enet_pads[] = {
  69         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  70         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  71         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  72         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  73         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  74         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  75         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  76         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
  77                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
  78         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
  79                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
  80         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  81         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  82         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  83         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  84         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  85         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
  86                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
  87         /* PHY nRST */
  88         IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
  89 };
  90
  91 /* NAND */
  92 static iomux_v3_cfg_t const nfc_pads[] = {
  93         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
  94         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
  95         IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  96         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  97         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  98         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
  99         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 100         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 101         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 102         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 103         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 104         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 105         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 106         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 107         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 108 };
 109
 110 #ifdef CONFIG_CMD_NAND
 111 static void setup_gpmi_nand(void)
 112 {
 113         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 114
 115         /* config gpmi nand iomux */
 116         SETUP_IOMUX_PADS(nfc_pads);
 117
 118         /* config gpmi and bch clock to 100 MHz */
 119         clrsetbits_le32(&mxc_ccm->cs2cdr,
 120                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 121                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 122                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 123                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 124                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 125                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 126
 127         /* enable gpmi and bch clock gating */
 128         setbits_le32(&mxc_ccm->CCGR4,
 129                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 130                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 131                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 132                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 133                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 134
 135         /* enable apbh clock gating */
 136         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 137 }
 138 #endif
 139
 140 static void setup_iomux_enet(int gpio)
 141 {
 142         SETUP_IOMUX_PADS(enet_pads);
 143
 144         /* toggle PHY_RST# */
 145         gpio_request(gpio, "phy_rst#");
 146         gpio_direction_output(gpio, 0);
 147         mdelay(2);
 148         gpio_set_value(gpio, 1);
 149 }
 150
 151 #ifdef CONFIG_USB_EHCI_MX6
 152 static iomux_v3_cfg_t const usb_pads[] = {
 153         IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID   | DIO_PAD_CFG),
 154         IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
 155         /* OTG PWR */
 156         IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22  | DIO_PAD_CFG),
 157 };
 158
 159 int board_ehci_hcd_init(int port)
 160 {
 161         int gpio;
 162
 163         SETUP_IOMUX_PADS(usb_pads);
 164
 165         /* Reset USB HUB */
 166         switch (board_type) {
 167         case GW53xx:
 168         case GW552x:
 169                 gpio = (IMX_GPIO_NR(1, 9));
 170                 break;
 171         case GW54proto:
 172         case GW54xx:
 173                 gpio = (IMX_GPIO_NR(1, 16));
 174                 break;
 175         default:
 176                 return 0;
 177         }
 178
 179         /* request and toggle hub rst */
 180         gpio_request(gpio, "usb_hub_rst#");
 181         gpio_direction_output(gpio, 0);
 182         mdelay(2);
 183         gpio_set_value(gpio, 1);
 184
 185         return 0;
 186 }
 187
 188 int board_ehci_power(int port, int on)
 189 {
 190         if (port)
 191                 return 0;
 192         gpio_set_value(GP_USB_OTG_PWR, on);
 193         return 0;
 194 }
 195 #endif /* CONFIG_USB_EHCI_MX6 */
 196
 197 #ifdef CONFIG_FSL_ESDHC
 198 static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
 199
 200 int board_mmc_getcd(struct mmc *mmc)
 201 {
 202         /* Card Detect */
 203         gpio_request(GP_SD3_CD, "sd_cd");
 204         gpio_direction_input(GP_SD3_CD);
 205         return !gpio_get_value(GP_SD3_CD);
 206 }
 207
 208 int board_mmc_init(bd_t *bis)
 209 {
 210         /* Only one USDHC controller on Ventana */
 211         SETUP_IOMUX_PADS(usdhc3_pads);
 212         usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 213         usdhc_cfg.max_bus_width = 4;
 214
 215         return fsl_esdhc_initialize(bis, &usdhc_cfg);
 216 }
 217 #endif /* CONFIG_FSL_ESDHC */
 218
 219 #ifdef CONFIG_MXC_SPI
 220 iomux_v3_cfg_t const ecspi1_pads[] = {
 221         /* SS1 */
 222         IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19  | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 223         IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 224         IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 225         IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 226 };
 227
 228 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 229 {
 230         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
 231 }
 232
 233 static void setup_spi(void)
 234 {
 235         gpio_request(IMX_GPIO_NR(3, 19), "spi_cs");
 236         gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
 237         SETUP_IOMUX_PADS(ecspi1_pads);
 238 }
 239 #endif
 240
 241 /* configure eth0 PHY board-specific LED behavior */
 242 int board_phy_config(struct phy_device *phydev)
 243 {
 244         unsigned short val;
 245
 246         /* Marvel 88E1510 */
 247         if (phydev->phy_id == 0x1410dd1) {
 248                 /*
 249                  * Page 3, Register 16: LED[2:0] Function Control Register
 250                  * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
 251                  * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
 252                  */
 253                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
 254                 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
 255                 val &= 0xff00;
 256                 val |= 0x0017;
 257                 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
 258                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
 259         }
 260
 261         if (phydev->drv->config)
 262                 phydev->drv->config(phydev);
 263
 264         return 0;
 265 }
 266
 267 int board_eth_init(bd_t *bis)
 268 {
 269 #ifdef CONFIG_FEC_MXC
 270         struct ventana_board_info *info = &ventana_info;
 271
 272         if (test_bit(EECONFIG_ETH0, info->config)) {
 273                 setup_iomux_enet(GP_PHY_RST);
 274                 cpu_eth_init(bis);
 275         }
 276 #endif
 277
 278 #ifdef CONFIG_E1000
 279         e1000_initialize(bis);
 280 #endif
 281
 282 #ifdef CONFIG_CI_UDC
 283         /* For otg ethernet*/
 284         usb_eth_initialize(bis);
 285 #endif
 286
 287         /* default to the first detected enet dev */
 288         if (!getenv("ethprime")) {
 289                 struct eth_device *dev = eth_get_dev_by_index(0);
 290                 if (dev) {
 291                         setenv("ethprime", dev->name);
 292                         printf("set ethprime to %s\n", getenv("ethprime"));
 293                 }
 294         }
 295
 296         return 0;
 297 }
 298
 299 #if defined(CONFIG_VIDEO_IPUV3)
 300
 301 static void enable_hdmi(struct display_info_t const *dev)
 302 {
 303         imx_enable_hdmi_phy();
 304 }
 305
 306 static int detect_i2c(struct display_info_t const *dev)
 307 {
 308         return i2c_set_bus_num(dev->bus) == 0 &&
 309                 i2c_probe(dev->addr) == 0;
 310 }
 311
 312 static void enable_lvds(struct display_info_t const *dev)
 313 {
 314         struct iomuxc *iomux = (struct iomuxc *)
 315                                 IOMUXC_BASE_ADDR;
 316
 317         /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
 318         u32 reg = readl(&iomux->gpr[2]);
 319         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 320         writel(reg, &iomux->gpr[2]);
 321
 322         /* Enable Backlight */
 323         gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
 324         gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
 325         gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
 326         SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
 327         gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
 328 }
 329
 330 struct display_info_t const displays[] = {{
 331         /* HDMI Output */
 332         .bus    = -1,
 333         .addr   = 0,
 334         .pixfmt = IPU_PIX_FMT_RGB24,
 335         .detect = detect_hdmi,
 336         .enable = enable_hdmi,
 337         .mode   = {
 338                 .name           = "HDMI",
 339                 .refresh        = 60,
 340                 .xres           = 1024,
 341                 .yres           = 768,
 342                 .pixclock       = 15385,
 343                 .left_margin    = 220,
 344                 .right_margin   = 40,
 345                 .upper_margin   = 21,
 346                 .lower_margin   = 7,
 347                 .hsync_len      = 60,
 348                 .vsync_len      = 10,
 349                 .sync           = FB_SYNC_EXT,
 350                 .vmode          = FB_VMODE_NONINTERLACED
 351 } }, {
 352         /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
 353         .bus    = 2,
 354         .addr   = 0x4,
 355         .pixfmt = IPU_PIX_FMT_LVDS666,
 356         .detect = detect_i2c,
 357         .enable = enable_lvds,
 358         .mode   = {
 359                 .name           = "Hannstar-XGA",
 360                 .refresh        = 60,
 361                 .xres           = 1024,
 362                 .yres           = 768,
 363                 .pixclock       = 15385,
 364                 .left_margin    = 220,
 365                 .right_margin   = 40,
 366                 .upper_margin   = 21,
 367                 .lower_margin   = 7,
 368                 .hsync_len      = 60,
 369                 .vsync_len      = 10,
 370                 .sync           = FB_SYNC_EXT,
 371                 .vmode          = FB_VMODE_NONINTERLACED
 372 } }, {
 373         /* DLC700JMG-T-4 */
 374         .bus    = 0,
 375         .addr   = 0,
 376         .detect = NULL,
 377         .enable = enable_lvds,
 378         .pixfmt = IPU_PIX_FMT_LVDS666,
 379         .mode   = {
 380                 .name           = "DLC700JMGT4",
 381                 .refresh        = 60,
 382                 .xres           = 1024,         /* 1024x600active pixels */
 383                 .yres           = 600,
 384                 .pixclock       = 15385,        /* 64MHz */
 385                 .left_margin    = 220,
 386                 .right_margin   = 40,
 387                 .upper_margin   = 21,
 388                 .lower_margin   = 7,
 389                 .hsync_len      = 60,
 390                 .vsync_len      = 10,
 391                 .sync           = FB_SYNC_EXT,
 392                 .vmode          = FB_VMODE_NONINTERLACED
 393 } }, {
 394         /* DLC800FIG-T-3 */
 395         .bus    = 0,
 396         .addr   = 0,
 397         .detect = NULL,
 398         .enable = enable_lvds,
 399         .pixfmt = IPU_PIX_FMT_LVDS666,
 400         .mode   = {
 401                 .name           = "DLC800FIGT3",
 402                 .refresh        = 60,
 403                 .xres           = 1024,         /* 1024x768 active pixels */
 404                 .yres           = 768,
 405                 .pixclock       = 15385,        /* 64MHz */
 406                 .left_margin    = 220,
 407                 .right_margin   = 40,
 408                 .upper_margin   = 21,
 409                 .lower_margin   = 7,
 410                 .hsync_len      = 60,
 411                 .vsync_len      = 10,
 412                 .sync           = FB_SYNC_EXT,
 413                 .vmode          = FB_VMODE_NONINTERLACED
 414 } } };
 415 size_t display_count = ARRAY_SIZE(displays);
 416
 417 static void setup_display(void)
 418 {
 419         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 420         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 421         int reg;
 422
 423         enable_ipu_clock();
 424         imx_setup_hdmi();
 425         /* Turn on LDB0,IPU,IPU DI0 clocks */
 426         reg = __raw_readl(&mxc_ccm->CCGR3);
 427         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 428         writel(reg, &mxc_ccm->CCGR3);
 429
 430         /* set LDB0, LDB1 clk select to 011/011 */
 431         reg = readl(&mxc_ccm->cs2cdr);
 432         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 433                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 434         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 435               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 436         writel(reg, &mxc_ccm->cs2cdr);
 437
 438         reg = readl(&mxc_ccm->cscmr2);
 439         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 440         writel(reg, &mxc_ccm->cscmr2);
 441
 442         reg = readl(&mxc_ccm->chsccdr);
 443         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 444                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 445         writel(reg, &mxc_ccm->chsccdr);
 446
 447         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 448              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 449              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 450              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 451              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 452              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 453              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 454              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 455              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 456         writel(reg, &iomux->gpr[2]);
 457
 458         reg = readl(&iomux->gpr[3]);
 459         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 460             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 461                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 462         writel(reg, &iomux->gpr[3]);
 463
 464         /* LVDS Backlight GPIO on LVDS connector - output low */
 465         SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
 466         gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
 467 }
 468 #endif /* CONFIG_VIDEO_IPUV3 */
 469
 470 /* setup board specific PMIC */
 471 int power_init_board(void)
 472 {
 473         setup_pmic();
 474         return 0;
 475 }
 476
 477 #if defined(CONFIG_CMD_PCI)
 478 int imx6_pcie_toggle_reset(void)
 479 {
 480         if (board_type < GW_UNKNOWN) {
 481                 uint pin = gpio_cfg[board_type].pcie_rst;
 482                 gpio_request(pin, "pci_rst#");
 483                 gpio_direction_output(pin, 0);
 484                 mdelay(50);
 485                 gpio_direction_output(pin, 1);
 486         }
 487         return 0;
 488 }
 489
 490 /*
 491  * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
 492  * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
 493  * properly and assert reset for 100ms.
 494  */
 495 void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
 496                          unsigned short vendor, unsigned short device,
 497                          unsigned short class)
 498 {
 499         u32 dw;
 500
 501         debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
 502               PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
 503         if (vendor == PCI_VENDOR_ID_PLX &&
 504             (device & 0xfff0) == 0x8600 &&
 505             PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
 506                 debug("configuring PLX 860X downstream PERST#\n");
 507                 pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
 508                 dw |= 0xaaa8; /* GPIO1-7 outputs */
 509                 pci_hose_write_config_dword(hose, dev, 0x62c, dw);
 510
 511                 pci_hose_read_config_dword(hose, dev, 0x644, &dw);
 512                 dw |= 0xfe;   /* GPIO1-7 output high */
 513                 pci_hose_write_config_dword(hose, dev, 0x644, dw);
 514
 515                 mdelay(100);
 516         }
 517 }
 518 #endif /* CONFIG_CMD_PCI */
 519
 520 #ifdef CONFIG_SERIAL_TAG
 521 /*
 522  * called when setting up ATAGS before booting kernel
 523  * populate serialnum from the following (in order of priority):
 524  *   serial# env var
 525  *   eeprom
 526  */
 527 void get_board_serial(struct tag_serialnr *serialnr)
 528 {
 529         char *serial = getenv("serial#");
 530
 531         if (serial) {
 532                 serialnr->high = 0;
 533                 serialnr->low = simple_strtoul(serial, NULL, 10);
 534         } else if (ventana_info.model[0]) {
 535                 serialnr->high = 0;
 536                 serialnr->low = ventana_info.serial;
 537         } else {
 538                 serialnr->high = 0;
 539                 serialnr->low = 0;
 540         }
 541 }
 542 #endif
 543
 544 /*
 545  * Board Support
 546  */
 547
 548 int board_early_init_f(void)
 549 {
 550         setup_iomux_uart();
 551
 552 #if defined(CONFIG_VIDEO_IPUV3)
 553         setup_display();
 554 #endif
 555         return 0;
 556 }
 557
 558 int dram_init(void)
 559 {
 560         gd->ram_size = imx_ddr_size();
 561         return 0;
 562 }
 563
 564 int board_init(void)
 565 {
 566         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 567
 568         clrsetbits_le32(&iomuxc_regs->gpr[1],
 569                         IOMUXC_GPR1_OTG_ID_MASK,
 570                         IOMUXC_GPR1_OTG_ID_GPIO1);
 571
 572         /* address of linux boot parameters */
 573         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 574
 575 #ifdef CONFIG_CMD_NAND
 576         setup_gpmi_nand();
 577 #endif
 578 #ifdef CONFIG_MXC_SPI
 579         setup_spi();
 580 #endif
 581         setup_ventana_i2c();
 582
 583 #ifdef CONFIG_CMD_SATA
 584         setup_sata();
 585 #endif
 586         /* read Gateworks EEPROM into global struct (used later) */
 587         board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
 588
 589         setup_iomux_gpio(board_type, &ventana_info);
 590
 591         return 0;
 592 }
 593
 594 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
 595 /*
 596  * called during late init (after relocation and after board_init())
 597  * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
 598  * EEPROM read.
 599  */
 600 int checkboard(void)
 601 {
 602         struct ventana_board_info *info = &ventana_info;
 603         unsigned char buf[4];
 604         const char *p;
 605         int quiet; /* Quiet or minimal output mode */
 606
 607         quiet = 0;
 608         p = getenv("quiet");
 609         if (p)
 610                 quiet = simple_strtol(p, NULL, 10);
 611         else
 612                 setenv("quiet", "0");
 613
 614         puts("\nGateworks Corporation Copyright 2014\n");
 615         if (info->model[0]) {
 616                 printf("Model: %s\n", info->model);
 617                 printf("MFGDate: %02x-%02x-%02x%02x\n",
 618                        info->mfgdate[0], info->mfgdate[1],
 619                        info->mfgdate[2], info->mfgdate[3]);
 620                 printf("Serial:%d\n", info->serial);
 621         } else {
 622                 puts("Invalid EEPROM - board will not function fully\n");
 623         }
 624         if (quiet)
 625                 return 0;
 626
 627         /* Display GSC firmware revision/CRC/status */
 628         gsc_info(0);
 629
 630         /* Display RTC */
 631         if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
 632                 printf("RTC:   %d\n",
 633                        buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
 634         }
 635
 636         return 0;
 637 }
 638 #endif
 639
 640 #ifdef CONFIG_CMD_BMODE
 641 /*
 642  * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
 643  * see Table 8-11 and Table 5-9
 644  *  BOOT_CFG1[7] = 1 (boot from NAND)
 645  *  BOOT_CFG1[5] = 0 - raw NAND
 646  *  BOOT_CFG1[4] = 0 - default pad settings
 647  *  BOOT_CFG1[3:2] = 00 - devices = 1
 648  *  BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
 649  *  BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
 650  *  BOOT_CFG2[2:1] = 01 - Pages In Block = 64
 651  *  BOOT_CFG2[0] = 0 - Reset time 12ms
 652  */
 653 static const struct boot_mode board_boot_modes[] = {
 654         /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
 655         { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
 656         { NULL, 0 },
 657 };
 658 #endif
 659
 660 /* late init */
 661 int misc_init_r(void)
 662 {
 663         struct ventana_board_info *info = &ventana_info;
 664
 665         /* set env vars based on EEPROM data */
 666         if (ventana_info.model[0]) {
 667                 char str[16], fdt[36];
 668                 char *p;
 669                 const char *cputype = "";
 670                 int i;
 671
 672                 /*
 673                  * FDT name will be prefixed with CPU type.  Three versions
 674                  * will be created each increasingly generic and bootloader
 675                  * env scripts will try loading each from most specific to
 676                  * least.
 677                  */
 678                 if (is_cpu_type(MXC_CPU_MX6Q) ||
 679                     is_cpu_type(MXC_CPU_MX6D))
 680                         cputype = "imx6q";
 681                 else if (is_cpu_type(MXC_CPU_MX6DL) ||
 682                          is_cpu_type(MXC_CPU_MX6SOLO))
 683                         cputype = "imx6dl";
 684                 setenv("soctype", cputype);
 685                 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
 686                         setenv("flash_layout", "large");
 687                 else
 688                         setenv("flash_layout", "normal");
 689                 memset(str, 0, sizeof(str));
 690                 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
 691                         str[i] = tolower(info->model[i]);
 692                 setenv("model", str);
 693                 if (!getenv("fdt_file")) {
 694                         sprintf(fdt, "%s-%s.dtb", cputype, str);
 695                         setenv("fdt_file", fdt);
 696                 }
 697                 p = strchr(str, '-');
 698                 if (p) {
 699                         *p++ = 0;
 700
 701                         setenv("model_base", str);
 702                         sprintf(fdt, "%s-%s.dtb", cputype, str);
 703                         setenv("fdt_file1", fdt);
 704                         if (board_type != GW551x &&
 705                             board_type != GW552x &&
 706                             board_type != GW553x)
 707                                 str[4] = 'x';
 708                         str[5] = 'x';
 709                         str[6] = 0;
 710                         sprintf(fdt, "%s-%s.dtb", cputype, str);
 711                         setenv("fdt_file2", fdt);
 712                 }
 713
 714                 /* initialize env from EEPROM */
 715                 if (test_bit(EECONFIG_ETH0, info->config) &&
 716                     !getenv("ethaddr")) {
 717                         eth_setenv_enetaddr("ethaddr", info->mac0);
 718                 }
 719                 if (test_bit(EECONFIG_ETH1, info->config) &&
 720                     !getenv("eth1addr")) {
 721                         eth_setenv_enetaddr("eth1addr", info->mac1);
 722                 }
 723
 724                 /* board serial-number */
 725                 sprintf(str, "%6d", info->serial);
 726                 setenv("serial#", str);
 727
 728                 /* memory MB */
 729                 sprintf(str, "%d", (int) (gd->ram_size >> 20));
 730                 setenv("mem_mb", str);
 731         }
 732
 733
 734         /* setup baseboard specific GPIO based on board and env */
 735         setup_board_gpio(board_type, info);
 736
 737 #ifdef CONFIG_CMD_BMODE
 738         add_board_boot_modes(board_boot_modes);
 739 #endif
 740
 741         /* disable boot watchdog */
 742         gsc_boot_wd_disable();
 743
 744         return 0;
 745 }
 746
 747 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 748
 749 static int ft_sethdmiinfmt(void *blob, char *mode)
 750 {
 751         int off;
 752
 753         if (!mode)
 754                 return -EINVAL;
 755
 756         off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
 757         if (off < 0)
 758                 return off;
 759
 760         if (0 == strcasecmp(mode, "yuv422bt656")) {
 761                 u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
 762                              0x00, 0x00, 0x00 };
 763                 mode = "422_ccir";
 764                 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
 765                 fdt_setprop_u32(blob, off, "vidout_trc", 1);
 766                 fdt_setprop_u32(blob, off, "vidout_blc", 1);
 767                 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
 768                 printf("   set HDMI input mode to %s\n", mode);
 769         } else if (0 == strcasecmp(mode, "yuv422smp")) {
 770                 u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
 771                              0x82, 0x81, 0x00 };
 772                 mode = "422_smp";
 773                 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
 774                 fdt_setprop_u32(blob, off, "vidout_trc", 0);
 775                 fdt_setprop_u32(blob, off, "vidout_blc", 0);
 776                 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
 777                 printf("   set HDMI input mode to %s\n", mode);
 778         } else {
 779                 return -EINVAL;
 780         }
 781
 782         return 0;
 783 }
 784
 785 /* enable a property of a node if the node is found */
 786 static inline void ft_enable_path(void *blob, const char *path)
 787 {
 788         int i = fdt_path_offset(blob, path);
 789         if (i >= 0) {
 790                 debug("enabling %s\n", path);
 791                 fdt_status_okay(blob, i);
 792         }
 793 }
 794
 795 /*
 796  * called prior to booting kernel or by 'fdt boardsetup' command
 797  *
 798  * unless 'fdt_noauto' env var is set we will update the following in the DTB:
 799  *  - mtd partitions based on mtdparts/mtdids env
 800  *  - system-serial (board serial num from EEPROM)
 801  *  - board (full model from EEPROM)
 802  *  - peripherals removed from DTB if not loaded on board (per EEPROM config)
 803  */
 804 int ft_board_setup(void *blob, bd_t *bd)
 805 {
 806         struct ventana_board_info *info = &ventana_info;
 807         struct ventana_eeprom_config *cfg;
 808         struct node_info nodes[] = {
 809                 { "sst,w25q256",          MTD_DEV_TYPE_NOR, },  /* SPI flash */
 810                 { "fsl,imx6q-gpmi-nand",  MTD_DEV_TYPE_NAND, }, /* NAND flash */
 811         };
 812         const char *model = getenv("model");
 813         const char *display = getenv("display");
 814         int i;
 815         char rev = 0;
 816
 817         /* determine board revision */
 818         for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
 819                 if (ventana_info.model[i] >= 'A') {
 820                         rev = ventana_info.model[i];
 821                         break;
 822                 }
 823         }
 824
 825         if (getenv("fdt_noauto")) {
 826                 puts("   Skiping ft_board_setup (fdt_noauto defined)\n");
 827                 return 0;
 828         }
 829
 830         if (test_bit(EECONFIG_NAND, info->config)) {
 831                 /* Update partition nodes using info from mtdparts env var */
 832                 puts("   Updating MTD partitions...\n");
 833                 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
 834         }
 835
 836         /* Update display timings from display env var */
 837         if (display) {
 838                 if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
 839                                       display) >= 0)
 840                         printf("   Set display timings for %s...\n", display);
 841         }
 842
 843         printf("   Adjusting FDT per EEPROM for %s...\n", model);
 844
 845         /* board serial number */
 846         fdt_setprop(blob, 0, "system-serial", getenv("serial#"),
 847                     strlen(getenv("serial#")) + 1);
 848
 849         /* board (model contains model from device-tree) */
 850         fdt_setprop(blob, 0, "board", info->model,
 851                     strlen((const char *)info->model) + 1);
 852
 853         /* set desired digital video capture format */
 854         ft_sethdmiinfmt(blob, getenv("hdmiinfmt"));
 855
 856         /*
 857          * disable serial2 node for GW54xx for compatibility with older
 858          * 3.10.x kernel that improperly had this node enabled in the DT
 859          */
 860         if (board_type == GW54xx) {
 861                 i = fdt_path_offset(blob,
 862                                     "/soc/aips-bus@02100000/serial@021ec000");
 863                 if (i)
 864                         fdt_del_node(blob, i);
 865         }
 866
 867         /*
 868          * disable wdog1/wdog2 nodes for GW51xx below revC to work around
 869          * errata causing wdog timer to be unreliable.
 870          */
 871         if (board_type == GW51xx && rev >= 'A' && rev < 'C') {
 872                 i = fdt_path_offset(blob,
 873                                     "/soc/aips-bus@02000000/wdog@020bc000");
 874                 if (i)
 875                         fdt_status_disabled(blob, i);
 876         }
 877
 878         /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
 879         else if (board_type == GW52xx && info->model[4] == '2') {
 880                 u32 handle = 0;
 881                 u32 *range = NULL;
 882
 883                 i = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
 884                 if (i)
 885                         range = (u32 *)fdt_getprop(blob, i, "reset-gpio",
 886                                                    NULL);
 887
 888                 if (range) {
 889                         i = fdt_path_offset(blob,
 890                                             "/soc/aips-bus@02000000/gpio@020a4000");
 891                         if (i)
 892                                 handle = fdt_get_phandle(blob, i);
 893                         if (handle) {
 894                                 range[0] = cpu_to_fdt32(handle);
 895                                 range[1] = cpu_to_fdt32(23);
 896                         }
 897                 }
 898         }
 899
 900         /*
 901          * isolate CSI0_DATA_EN for GW551x below revB to work around
 902          * errata causing non functional digital video in (it is not hooked up)
 903          */
 904         else if (board_type == GW551x && rev == 'A') {
 905                 u32 *range = NULL;
 906                 int len;
 907                 const u32 *handle = NULL;
 908
 909                 i = fdt_node_offset_by_compatible(blob, -1,
 910                                                   "fsl,imx-tda1997x-video");
 911                 if (i)
 912                         handle = fdt_getprop(blob, i, "pinctrl-0", NULL);
 913                 if (handle)
 914                         i = fdt_node_offset_by_phandle(blob,
 915                                                        fdt32_to_cpu(*handle));
 916                 if (i)
 917                         range = (u32 *)fdt_getprop(blob, i, "fsl,pins", &len);
 918                 if (range) {
 919                         len /= sizeof(u32);
 920                         for (i = 0; i < len; i += 6) {
 921                                 u32 mux_reg = fdt32_to_cpu(range[i+0]);
 922                                 u32 conf_reg = fdt32_to_cpu(range[i+1]);
 923                                 /* mux PAD_CSI0_DATA_EN to GPIO */
 924                                 if (is_cpu_type(MXC_CPU_MX6Q) &&
 925                                     mux_reg == 0x260 && conf_reg == 0x630)
 926                                         range[i+3] = cpu_to_fdt32(0x5);
 927                                 else if (!is_cpu_type(MXC_CPU_MX6Q) &&
 928                                     mux_reg == 0x08c && conf_reg == 0x3a0)
 929                                         range[i+3] = cpu_to_fdt32(0x5);
 930                         }
 931                         fdt_setprop_inplace(blob, i, "fsl,pins", range, len);
 932                 }
 933
 934                 /* set BT656 video format */
 935                 ft_sethdmiinfmt(blob, "yuv422bt656");
 936         }
 937
 938         /* Configure DIO */
 939         for (i = 0; i < gpio_cfg[board_type].num_gpios; i++) {
 940                 struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
 941                 char arg[10];
 942
 943                 sprintf(arg, "dio%d", i);
 944                 if (!hwconfig(arg))
 945                         continue;
 946                 if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
 947                 {
 948                         char path[48];
 949                         sprintf(path, "/soc/aips-bus@02000000/pwm@%08x",
 950                                 0x02080000 + (0x4000 * (cfg->pwm_param - 1)));
 951                         printf("   Enabling pwm%d for DIO%d\n",
 952                                cfg->pwm_param, i);
 953                         ft_enable_path(blob, path);
 954                 }
 955         }
 956
 957         /*
 958          * Peripheral Config:
 959          *  remove nodes by alias path if EEPROM config tells us the
 960          *  peripheral is not loaded on the board.
 961          */
 962         if (getenv("fdt_noconfig")) {
 963                 puts("   Skiping periperhal config (fdt_noconfig defined)\n");
 964                 return 0;
 965         }
 966         cfg = econfig;
 967         while (cfg->name) {
 968                 if (!test_bit(cfg->bit, info->config)) {
 969                         fdt_del_node_and_alias(blob, cfg->dtalias ?
 970                                                cfg->dtalias : cfg->name);
 971                 }
 972                 cfg++;
 973         }
 974
 975         return 0;
 976 }
 977 #endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
 978
 979 static struct mxc_serial_platdata ventana_mxc_serial_plat = {
 980         .reg = (struct mxc_uart *)UART2_BASE,
 981 };
 982
 983 U_BOOT_DEVICE(ventana_serial) = {
 984         .name   = "serial_mxc",
 985         .platdata = &ventana_mxc_serial_plat,
 986 };