1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013 Gateworks Corporation
5 * Author: Tim Harvey <tharvey@gateworks.com>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/mx6-pins.h>
12 #include <asm/arch/mxc_hdmi.h>
13 #include <asm/arch/sys_proto.h>
14 #include <asm/global_data.h>
16 #include <asm/mach-imx/boot_mode.h>
17 #include <asm/mach-imx/video.h>
18 #include <asm/setup.h>
21 #include <linux/ctype.h>
24 #include <linux/delay.h>
25 #include <power/pmic.h>
26 #include <fdt_support.h>
27 #include <jffs2/load_kernel.h>
32 DECLARE_GLOBAL_DATA_PTR;
36 * EEPROM board info struct populated by read_eeprom so that we only have to
39 struct ventana_board_info ventana_info;
40 static int board_type;
42 #ifdef CONFIG_USB_EHCI_MX6
43 /* toggle USB_HUB_RST# for boards that have it; it is not defined in dt */
44 int board_ehci_hcd_init(int port)
48 /* USB HUB is always on P1 */
57 gpio = (IMX_GPIO_NR(1, 9));
61 gpio = (IMX_GPIO_NR(1, 16));
67 /* request and toggle hub rst */
68 gpio_request(gpio, "usb_hub_rst#");
69 gpio_direction_output(gpio, 0);
71 gpio_set_value(gpio, 1);
75 #endif /* CONFIG_USB_EHCI_MX6 */
77 /* configure eth0 PHY board-specific LED behavior */
78 int board_phy_config(struct phy_device *phydev)
83 if (phydev->phy_id == 0x1410dd1) {
86 * Page 3, Register 16: LED[2:0] Function Control Register
87 * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
88 * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
90 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
91 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
94 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
95 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
99 else if (phydev->phy_id == 0x2000a231) {
101 /* LED configuration */
103 val |= 0x5 << 4; /* LED1(Amber;Speed) : 1000BT link */
104 val |= 0xb << 8; /* LED2(Green;Link/Act): blink for TX/RX act */
105 phy_write(phydev, MDIO_DEVAD_NONE, 24, val);
107 /* configure register 0x170 for ref CLKOUT */
108 phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x001f);
109 phy_write(phydev, MDIO_DEVAD_NONE, 14, 0x0170);
110 phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x401f);
111 val = phy_read(phydev, MDIO_DEVAD_NONE, 14);
113 val |= 0x0b00; /* chD tx clock*/
114 phy_write(phydev, MDIO_DEVAD_NONE, 14, val);
117 if (phydev->drv->config)
118 phydev->drv->config(phydev);
123 #ifdef CONFIG_MV88E61XX_SWITCH
124 int mv88e61xx_hw_reset(struct phy_device *phydev)
126 struct mii_dev *bus = phydev->bus;
128 /* GPIO[0] output, CLK125 */
129 debug("enabling RGMII_REFCLK\n");
130 bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
131 0x1a /*MV_SCRATCH_MISC*/,
132 (1 << 15) | (0x62 /*MV_GPIO_DIR*/ << 8) | 0xfe);
133 bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
134 0x1a /*MV_SCRATCH_MISC*/,
135 (1 << 15) | (0x68 /*MV_GPIO01_CNTL*/ << 8) | 7);
137 /* RGMII delay - Physical Control register bit[15:14] */
138 debug("setting port%d RGMII rx/tx delay\n", CONFIG_MV88E61XX_CPU_PORT);
139 /* forced 1000mbps full-duplex link */
140 bus->write(bus, 0x10 + CONFIG_MV88E61XX_CPU_PORT, 0, 1, 0xc0fe);
141 phydev->autoneg = AUTONEG_DISABLE;
142 phydev->speed = SPEED_1000;
143 phydev->duplex = DUPLEX_FULL;
145 /* LED configuration: 7:4-green (8=Activity) 3:0 amber (8=Link) */
146 bus->write(bus, 0x10, 0, 0x16, 0x8088);
147 bus->write(bus, 0x11, 0, 0x16, 0x8088);
148 bus->write(bus, 0x12, 0, 0x16, 0x8088);
149 bus->write(bus, 0x13, 0, 0x16, 0x8088);
153 #endif // CONFIG_MV88E61XX_SWITCH
155 #if defined(CONFIG_VIDEO_IPUV3)
156 static void enable_hdmi(struct display_info_t const *dev)
158 imx_enable_hdmi_phy();
161 static int detect_lvds(struct display_info_t const *dev)
163 /* only the following boards support LVDS connectors */
164 switch (board_type) {
176 return i2c_set_bus_num(dev->bus) == 0 &&
177 i2c_probe(dev->addr) == 0;
180 static void enable_lvds(struct display_info_t const *dev)
182 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
184 /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
185 u32 reg = readl(&iomux->gpr[2]);
186 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
187 writel(reg, &iomux->gpr[2]);
190 switch (board_type) {
194 if (!strncmp(dev->mode.name, "Hannstar", 8)) {
195 SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
196 gpio_request(IMX_GPIO_NR(1, 10), "cabc");
197 gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
198 } else if (!strncmp(dev->mode.name, "DLC", 3)) {
199 SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
200 gpio_request(IMX_GPIO_NR(1, 10), "touch_rst#");
201 gpio_direction_output(IMX_GPIO_NR(1, 10), 1);
208 /* Configure backlight */
209 gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
210 SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
211 gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
214 struct display_info_t const displays[] = {{
218 .pixfmt = IPU_PIX_FMT_RGB24,
219 .detect = detect_hdmi,
220 .enable = enable_hdmi,
234 .vmode = FB_VMODE_NONINTERLACED
236 /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
239 .pixfmt = IPU_PIX_FMT_LVDS666,
240 .detect = detect_lvds,
241 .enable = enable_lvds,
243 .name = "Hannstar-XGA",
255 .vmode = FB_VMODE_NONINTERLACED
260 .detect = detect_lvds,
261 .enable = enable_lvds,
262 .pixfmt = IPU_PIX_FMT_LVDS666,
264 .name = "DLC700JMGT4",
266 .xres = 1024, /* 1024x600active pixels */
268 .pixclock = 15385, /* 64MHz */
276 .vmode = FB_VMODE_NONINTERLACED
278 /* DLC0700XDP21LF-C-1 */
281 .detect = detect_lvds,
282 .enable = enable_lvds,
283 .pixfmt = IPU_PIX_FMT_LVDS666,
285 .name = "DLC0700XDP21LF",
287 .xres = 1024, /* 1024x600active pixels */
289 .pixclock = 15385, /* 64MHz */
297 .vmode = FB_VMODE_NONINTERLACED
302 .detect = detect_lvds,
303 .enable = enable_lvds,
304 .pixfmt = IPU_PIX_FMT_LVDS666,
306 .name = "DLC800FIGT3",
308 .xres = 1024, /* 1024x768 active pixels */
310 .pixclock = 15385, /* 64MHz */
318 .vmode = FB_VMODE_NONINTERLACED
322 .detect = detect_lvds,
323 .enable = enable_lvds,
324 .pixfmt = IPU_PIX_FMT_LVDS666,
330 .pixclock = 15385, /* 64MHz */
338 .vmode = FB_VMODE_NONINTERLACED
342 size_t display_count = ARRAY_SIZE(displays);
344 static void setup_display(void)
346 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
347 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
352 /* Turn on LDB0,IPU,IPU DI0 clocks */
353 reg = __raw_readl(&mxc_ccm->CCGR3);
354 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
355 writel(reg, &mxc_ccm->CCGR3);
357 /* set LDB0, LDB1 clk select to 011/011 */
358 reg = readl(&mxc_ccm->cs2cdr);
359 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
360 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
361 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
362 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
363 writel(reg, &mxc_ccm->cs2cdr);
365 reg = readl(&mxc_ccm->cscmr2);
366 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
367 writel(reg, &mxc_ccm->cscmr2);
369 reg = readl(&mxc_ccm->chsccdr);
370 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
371 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
372 writel(reg, &mxc_ccm->chsccdr);
374 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
375 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
376 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
377 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
378 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
379 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
380 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
381 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
382 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
383 writel(reg, &iomux->gpr[2]);
385 reg = readl(&iomux->gpr[3]);
386 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
387 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
388 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
389 writel(reg, &iomux->gpr[3]);
391 #endif /* CONFIG_VIDEO_IPUV3 */
393 /* setup board specific PMIC */
394 int power_init_board(void)
401 * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
402 * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
403 * properly and assert reset for 100ms.
405 #define MAX_PCI_DEVS 32
409 unsigned short vendor;
410 unsigned short device;
411 unsigned short class;
412 unsigned short busno; /* subbordinate busno */
413 struct pci_dev *ppar;
415 struct pci_dev pci_devs[MAX_PCI_DEVS];
419 void board_pci_fixup_dev(struct udevice *bus, struct udevice *udev)
421 struct pci_child_plat *pdata = dev_get_parent_plat(udev);
422 struct pci_dev *pdev = &pci_devs[pci_devno++];
423 unsigned short vendor = pdata->vendor;
424 unsigned short device = pdata->device;
425 unsigned int class = pdata->class;
426 pci_dev_t dev = dm_pci_get_bdf(udev);
429 debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
430 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
432 /* store array of devs for later use in device-tree fixup */
435 pdev->vendor = vendor;
436 pdev->device = device;
439 if (class == PCI_CLASS_BRIDGE_PCI)
440 pdev->busno = ++pci_bridgeno;
444 /* fixup RC - it should be 00:00.0 not 00:01.0 */
445 if (PCI_BUS(dev) == 0)
448 /* find dev's parent */
449 for (i = 0; i < pci_devno; i++) {
450 if (pci_devs[i].busno == PCI_BUS(pdev->devfn)) {
451 pdev->ppar = &pci_devs[i];
456 /* assert downstream PERST# */
457 if (vendor == PCI_VENDOR_ID_PLX &&
458 (device & 0xfff0) == 0x8600 &&
459 PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
461 debug("configuring PLX 860X downstream PERST#\n");
462 pci_bus_read_config(bus, dev, 0x62c, &val, PCI_SIZE_32);
463 val |= 0xaaa8; /* GPIO1-7 outputs */
464 pci_bus_write_config(bus, dev, 0x62c, val, PCI_SIZE_32);
466 pci_bus_read_config(bus, dev, 0x644, &val, PCI_SIZE_32);
467 val |= 0xfe; /* GPIO1-7 output high */
468 pci_bus_write_config(bus, dev, 0x644, val, PCI_SIZE_32);
474 #ifdef CONFIG_SERIAL_TAG
476 * called when setting up ATAGS before booting kernel
477 * populate serialnum from the following (in order of priority):
481 void get_board_serial(struct tag_serialnr *serialnr)
483 char *serial = env_get("serial#");
487 serialnr->low = dectoul(serial, NULL);
488 } else if (ventana_info.model[0]) {
490 serialnr->low = ventana_info.serial;
502 int board_early_init_f(void)
504 #if defined(CONFIG_VIDEO_IPUV3)
512 gd->ram_size = imx_ddr_size();
518 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
520 clrsetbits_le32(&iomuxc_regs->gpr[1],
521 IOMUXC_GPR1_OTG_ID_MASK,
522 IOMUXC_GPR1_OTG_ID_GPIO1);
524 /* address of linux boot parameters */
525 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
527 /* read Gateworks EEPROM into global struct (used later) */
528 setup_ventana_i2c(0);
529 board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
531 setup_ventana_i2c(1);
532 setup_ventana_i2c(2);
534 setup_iomux_gpio(board_type, &ventana_info);
539 int board_fit_config_name_match(const char *name)
547 dtb = gsc_get_dtb_name(i++, buf, sizeof(buf));
548 if (dtb && !strcmp(dtb, name)) {
550 printf("DTB: %s\n", name);
558 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
560 * called during late init (after relocation and after board_init())
561 * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
566 struct ventana_board_info *info = &ventana_info;
567 unsigned char buf[4];
569 int quiet; /* Quiet or minimal output mode */
572 p = env_get("quiet");
574 quiet = simple_strtol(p, NULL, 10);
576 env_set("quiet", "0");
578 puts("\nGateworks Corporation Copyright 2014\n");
579 if (info->model[0]) {
580 printf("Model: %s\n", info->model);
581 printf("MFGDate: %02x-%02x-%02x%02x\n",
582 info->mfgdate[0], info->mfgdate[1],
583 info->mfgdate[2], info->mfgdate[3]);
584 printf("Serial:%d\n", info->serial);
586 puts("Invalid EEPROM - board will not function fully\n");
591 /* Display GSC firmware revision/CRC/status */
595 if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
597 buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
604 #ifdef CONFIG_CMD_BMODE
606 * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
607 * see Table 8-11 and Table 5-9
608 * BOOT_CFG1[7] = 1 (boot from NAND)
609 * BOOT_CFG1[5] = 0 - raw NAND
610 * BOOT_CFG1[4] = 0 - default pad settings
611 * BOOT_CFG1[3:2] = 00 - devices = 1
612 * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
613 * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
614 * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
615 * BOOT_CFG2[0] = 0 - Reset time 12ms
617 static const struct boot_mode board_boot_modes[] = {
618 /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
619 { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
620 { "emmc2", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00) }, /* GW5600 */
621 { "emmc3", MAKE_CFGVAL(0x60, 0x50, 0x00, 0x00) }, /* GW5903/4/5 */
627 int misc_init_r(void)
629 struct ventana_board_info *info = &ventana_info;
633 /* set env vars based on EEPROM data */
634 if (ventana_info.model[0]) {
635 char str[16], fdt[36];
637 const char *cputype = "";
640 * FDT name will be prefixed with CPU type. Three versions
641 * will be created each increasingly generic and bootloader
642 * env scripts will try loading each from most specific to
645 if (is_cpu_type(MXC_CPU_MX6Q) ||
646 is_cpu_type(MXC_CPU_MX6D))
648 else if (is_cpu_type(MXC_CPU_MX6DL) ||
649 is_cpu_type(MXC_CPU_MX6SOLO))
651 env_set("soctype", cputype);
652 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
653 env_set("flash_layout", "large");
655 env_set("flash_layout", "normal");
656 memset(str, 0, sizeof(str));
657 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
658 str[i] = tolower(info->model[i]);
659 env_set("model", str);
660 if (!env_get("fdt_file")) {
661 sprintf(fdt, "%s-%s.dtb", cputype, str);
662 env_set("fdt_file", fdt);
664 p = strchr(str, '-');
668 env_set("model_base", str);
669 sprintf(fdt, "%s-%s.dtb", cputype, str);
670 env_set("fdt_file1", fdt);
671 if (board_type != GW551x &&
672 board_type != GW552x &&
673 board_type != GW553x &&
674 board_type != GW560x)
678 sprintf(fdt, "%s-%s.dtb", cputype, str);
679 env_set("fdt_file2", fdt);
682 /* initialize env from EEPROM */
683 if (test_bit(EECONFIG_ETH0, info->config) &&
684 !env_get("ethaddr")) {
685 eth_env_set_enetaddr("ethaddr", info->mac0);
687 if (test_bit(EECONFIG_ETH1, info->config) &&
688 !env_get("eth1addr")) {
689 eth_env_set_enetaddr("eth1addr", info->mac1);
692 /* board serial-number */
693 sprintf(str, "%6d", info->serial);
694 env_set("serial#", str);
697 sprintf(str, "%d", (int) (gd->ram_size >> 20));
698 env_set("mem_mb", str);
701 /* Set a non-initialized hwconfig based on board configuration */
702 if (!strcmp(env_get("hwconfig"), "_UNKNOWN_")) {
704 if (gpio_cfg[board_type].rs232_en)
705 strcat(buf, "rs232;");
706 for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
708 sprintf(buf1, "dio%d:mode=gpio;", i);
709 if (strlen(buf) + strlen(buf1) < sizeof(buf))
712 env_set("hwconfig", buf);
715 /* setup baseboard specific GPIO based on board and env */
716 setup_board_gpio(board_type, info);
718 #ifdef CONFIG_CMD_BMODE
719 add_board_boot_modes(board_boot_modes);
722 /* disable boot watchdog */
723 gsc_boot_wd_disable();
728 #ifdef CONFIG_OF_BOARD_SETUP
730 static int ft_sethdmiinfmt(void *blob, char *mode)
737 off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
741 if (0 == strcasecmp(mode, "yuv422bt656")) {
742 u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
745 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
746 fdt_setprop_u32(blob, off, "vidout_trc", 1);
747 fdt_setprop_u32(blob, off, "vidout_blc", 1);
748 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
749 printf(" set HDMI input mode to %s\n", mode);
750 } else if (0 == strcasecmp(mode, "yuv422smp")) {
751 u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
754 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
755 fdt_setprop_u32(blob, off, "vidout_trc", 0);
756 fdt_setprop_u32(blob, off, "vidout_blc", 0);
757 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
758 printf(" set HDMI input mode to %s\n", mode);
766 #if defined(CONFIG_CMD_PCI)
767 #define PCI_ID(x) ( \
768 (PCI_BUS(x->devfn)<<16)| \
769 (PCI_DEV(x->devfn)<<11)| \
770 (PCI_FUNC(x->devfn)<<8) \
772 int fdt_add_pci_node(void *blob, int par, struct pci_dev *dev)
778 sprintf(node, "pcie@%d,%d,%d", PCI_BUS(dev->devfn),
779 PCI_DEV(dev->devfn), PCI_FUNC(dev->devfn));
781 np = fdt_subnode_offset(blob, par, node);
784 np = fdt_add_subnode(blob, par, node);
786 printf(" %s failed: no space\n", __func__);
790 memset(reg, 0, sizeof(reg));
791 reg[0] = cpu_to_fdt32(PCI_ID(dev));
792 fdt_setprop(blob, np, "reg", reg, sizeof(reg));
797 /* build a path of nested PCI devs for all bridges passed through */
798 int fdt_add_pci_path(void *blob, struct pci_dev *dev)
800 struct pci_dev *bridges[MAX_PCI_DEVS];
803 /* build list of parents */
804 np = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
814 /* now add them the to DT in reverse order */
816 np = fdt_add_pci_node(blob, np, bridges[k]);
825 * The GW16082 has a hardware errata errata such that it's
826 * INTA/B/C/D are mis-mapped to its four slots (slot12-15). Because
827 * of this normal PCI interrupt swizzling will not work so we will
828 * provide an irq-map via device-tree.
830 int fdt_fixup_gw16082(void *blob, int np, struct pci_dev *dev)
834 uint32_t imap_new[8*4*4];
835 const uint32_t *imap;
840 /* build irq-map based on host controllers map */
841 host = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
843 printf(" %s failed: missing host\n", __func__);
847 /* use interrupt data from root complex's node */
848 imap = fdt_getprop(blob, host, "interrupt-map", &len);
849 if (!imap || len != 128) {
850 printf(" %s failed: invalid interrupt-map\n",
852 return -FDT_ERR_NOTFOUND;
855 /* obtain irq's of host controller in pin order */
856 for (i = 0; i < 4; i++)
857 irq[(fdt32_to_cpu(imap[(i*8)+3])-1)%4] = imap[(i*8)+6];
860 * determine number of swizzles necessary:
861 * For each bridge we pass through we need to swizzle
862 * the number of the slot we are on.
868 while(d && d->ppar) {
869 b += PCI_DEV(d->devfn);
873 /* create new irq mappings for slots12-15
874 * <skt> <idsel> <slot> <skt-inta> <skt-intb>
875 * J3 AD28 12 INTD INTA
876 * J4 AD29 13 INTC INTD
877 * J5 AD30 14 INTB INTC
878 * J2 AD31 15 INTA INTB
880 for (i = 0; i < 4; i++) {
881 /* addr matches bus:dev:func */
882 u32 addr = dev->busno << 16 | (12+i) << 11;
884 /* default cells from root complex */
885 memcpy(&imap_new[i*32], imap, 128);
886 /* first cell is PCI device address (BDF) */
887 imap_new[(i*32)+(0*8)+0] = cpu_to_fdt32(addr);
888 imap_new[(i*32)+(1*8)+0] = cpu_to_fdt32(addr);
889 imap_new[(i*32)+(2*8)+0] = cpu_to_fdt32(addr);
890 imap_new[(i*32)+(3*8)+0] = cpu_to_fdt32(addr);
891 /* third cell is pin */
892 imap_new[(i*32)+(0*8)+3] = cpu_to_fdt32(1);
893 imap_new[(i*32)+(1*8)+3] = cpu_to_fdt32(2);
894 imap_new[(i*32)+(2*8)+3] = cpu_to_fdt32(3);
895 imap_new[(i*32)+(3*8)+3] = cpu_to_fdt32(4);
896 /* sixth cell is relative interrupt */
897 imap_new[(i*32)+(0*8)+6] = irq[(15-(12+i)+b+0)%4];
898 imap_new[(i*32)+(1*8)+6] = irq[(15-(12+i)+b+1)%4];
899 imap_new[(i*32)+(2*8)+6] = irq[(15-(12+i)+b+2)%4];
900 imap_new[(i*32)+(3*8)+6] = irq[(15-(12+i)+b+3)%4];
902 fdt_setprop(blob, np, "interrupt-map", imap_new,
904 reg[0] = cpu_to_fdt32(0xfff00);
907 reg[3] = cpu_to_fdt32(0x7);
908 fdt_setprop(blob, np, "interrupt-map-mask", reg, sizeof(reg));
909 fdt_setprop_cell(blob, np, "#interrupt-cells", 1);
910 fdt_setprop_string(blob, np, "device_type", "pci");
911 fdt_setprop_cell(blob, np, "#address-cells", 3);
912 fdt_setprop_cell(blob, np, "#size-cells", 2);
913 printf(" Added custom interrupt-map for GW16082\n");
918 /* The sky2 GigE MAC obtains it's MAC addr from device-tree by default */
919 int fdt_fixup_sky2(void *blob, int np, struct pci_dev *dev)
923 unsigned char mac_addr[6];
926 sprintf(mac, "eth1addr");
929 for (j = 0; j < 6; j++) {
931 hextoul(tmp, &end) : 0;
933 tmp = (*end) ? end+1 : end;
935 fdt_setprop(blob, np, "local-mac-address", mac_addr,
937 printf(" Added mac addr for eth1\n");
945 * PCI DT nodes must be nested therefore if we need to apply a DT fixup
946 * we will walk the PCI bus and add bridge nodes up to the device receiving
949 void ft_board_pci_fixup(void *blob, struct bd_info *bd)
954 for (i = 0; i < pci_devno; i++) {
958 * The GW16082 consists of a TI XIO2001 PCIe-to-PCI bridge and
959 * an EEPROM at i2c1-0x50.
961 if ((dev->vendor == PCI_VENDOR_ID_TI) &&
962 (dev->device == 0x8240) &&
963 (i2c_set_bus_num(1) == 0) &&
964 (i2c_probe(0x50) == 0))
966 np = fdt_add_pci_path(blob, dev);
968 fdt_fixup_gw16082(blob, np, dev);
971 /* ethernet1 mac address */
972 else if ((dev->vendor == PCI_VENDOR_ID_MARVELL) &&
973 (dev->device == 0x4380))
975 np = fdt_add_pci_path(blob, dev);
977 fdt_fixup_sky2(blob, np, dev);
981 #endif /* if defined(CONFIG_CMD_PCI) */
984 * called prior to booting kernel or by 'fdt boardsetup' command
986 * unless 'fdt_noauto' env var is set we will update the following in the DTB:
987 * - mtd partitions based on mtdparts/mtdids env
988 * - system-serial (board serial num from EEPROM)
989 * - board (full model from EEPROM)
990 * - peripherals removed from DTB if not loaded on board (per EEPROM config)
992 #define PWM0_ADDR 0x2080000
993 int ft_board_setup(void *blob, struct bd_info *bd)
995 struct ventana_board_info *info = &ventana_info;
996 struct ventana_eeprom_config *cfg;
997 static const struct node_info nand_nodes[] = {
998 { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */
999 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
1001 const char *model = env_get("model");
1002 const char *display = env_get("display");
1006 /* determine board revision */
1007 for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
1008 if (ventana_info.model[i] >= 'A') {
1009 rev = ventana_info.model[i];
1014 if (env_get("fdt_noauto")) {
1015 puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
1019 /* Update MTD partition nodes using info from mtdparts env var */
1020 puts(" Updating MTD partitions...\n");
1021 fdt_fixup_mtdparts(blob, nand_nodes, ARRAY_SIZE(nand_nodes));
1023 /* Update display timings from display env var */
1025 if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
1027 printf(" Set display timings for %s...\n", display);
1030 printf(" Adjusting FDT per EEPROM for %s...\n", model);
1032 /* board serial number */
1033 fdt_setprop(blob, 0, "system-serial", env_get("serial#"),
1034 strlen(env_get("serial#")) + 1);
1036 /* board (model contains model from device-tree) */
1037 fdt_setprop(blob, 0, "board", info->model,
1038 strlen((const char *)info->model) + 1);
1040 /* set desired digital video capture format */
1041 ft_sethdmiinfmt(blob, env_get("hdmiinfmt"));
1043 /* early board/revision ft fixups */
1044 ft_early_fixup(blob, board_type);
1047 for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
1048 struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
1051 sprintf(arg, "dio%d", i);
1054 if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
1059 printf(" Enabling pwm%d for DIO%d\n",
1061 addr = PWM0_ADDR + (0x4000 * (cfg->pwm_param - 1));
1062 off = fdt_node_offset_by_compat_reg(blob,
1066 fdt_status_okay(blob, off);
1070 #if defined(CONFIG_CMD_PCI)
1071 if (!env_get("nopcifixup"))
1072 ft_board_pci_fixup(blob, bd);
1076 * remove reset gpio control as we configure the PHY registers
1077 * for internal delay, LED config, and clock config in the bootloader
1079 i = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-fec");
1081 fdt_delprop(blob, i, "phy-reset-gpios");
1084 * Peripheral Config:
1085 * remove nodes by alias path if EEPROM config tells us the
1086 * peripheral is not loaded on the board.
1088 if (env_get("fdt_noconfig")) {
1089 puts(" Skiping periperhal config (fdt_noconfig defined)\n");
1094 if (!test_bit(cfg->bit, info->config)) {
1095 fdt_del_node_and_alias(blob, cfg->dtalias ?
1096 cfg->dtalias : cfg->name);
1103 #endif /* CONFIG_OF_BOARD_SETUP */