2 * Copyright (C) 2013 Gateworks Corporation
4 * Author: Tim Harvey <tharvey@gateworks.com>
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clock.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/arch/iomux.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/arch/mxc_hdmi.h>
15 #include <asm/arch/sys_proto.h>
17 #include <asm/imx-common/boot_mode.h>
18 #include <asm/imx-common/sata.h>
19 #include <asm/imx-common/spi.h>
20 #include <asm/imx-common/video.h>
23 #include <dm/platform_data/serial_mxc.h>
26 #include <fdt_support.h>
27 #include <fsl_esdhc.h>
28 #include <jffs2/load_kernel.h>
29 #include <linux/ctype.h>
34 #include <power/pmic.h>
35 #include <power/ltc3676_pmic.h>
36 #include <power/pfuze100_pmic.h>
37 #include <fdt_support.h>
38 #include <jffs2/load_kernel.h>
39 #include <spi_flash.h>
44 DECLARE_GLOBAL_DATA_PTR;
48 * EEPROM board info struct populated by read_eeprom so that we only have to
51 struct ventana_board_info ventana_info;
53 static int board_type;
56 static iomux_v3_cfg_t const enet_pads[] = {
57 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
58 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
59 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
60 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
61 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
62 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
63 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
64 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
65 MUX_PAD_CTRL(ENET_PAD_CTRL)),
66 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
67 MUX_PAD_CTRL(ENET_PAD_CTRL)),
68 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
69 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
70 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
71 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
72 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
73 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
74 MUX_PAD_CTRL(ENET_PAD_CTRL)),
76 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
80 static iomux_v3_cfg_t const nfc_pads[] = {
81 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
82 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
83 IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
84 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
85 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
86 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
87 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
88 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
89 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
90 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
91 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
92 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
93 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
94 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
95 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
98 #ifdef CONFIG_CMD_NAND
99 static void setup_gpmi_nand(void)
101 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
103 /* config gpmi nand iomux */
104 SETUP_IOMUX_PADS(nfc_pads);
106 /* config gpmi and bch clock to 100 MHz */
107 clrsetbits_le32(&mxc_ccm->cs2cdr,
108 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
109 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
110 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
111 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
112 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
113 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
115 /* enable gpmi and bch clock gating */
116 setbits_le32(&mxc_ccm->CCGR4,
117 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
118 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
119 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
120 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
121 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
123 /* enable apbh clock gating */
124 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
128 static void setup_iomux_enet(int gpio)
130 SETUP_IOMUX_PADS(enet_pads);
132 /* toggle PHY_RST# */
133 gpio_request(gpio, "phy_rst#");
134 gpio_direction_output(gpio, 0);
136 gpio_set_value(gpio, 1);
140 #ifdef CONFIG_USB_EHCI_MX6
141 static iomux_v3_cfg_t const usb_pads[] = {
142 IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG),
143 IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
145 IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | DIO_PAD_CFG),
148 int board_ehci_hcd_init(int port)
152 SETUP_IOMUX_PADS(usb_pads);
155 switch (board_type) {
158 gpio = (IMX_GPIO_NR(1, 9));
162 gpio = (IMX_GPIO_NR(1, 16));
168 /* request and toggle hub rst */
169 gpio_request(gpio, "usb_hub_rst#");
170 gpio_direction_output(gpio, 0);
172 gpio_set_value(gpio, 1);
177 int board_ehci_power(int port, int on)
179 /* enable OTG VBUS */
180 if (!port && board_type < GW_UNKNOWN) {
181 if (gpio_cfg[board_type].otgpwr_en)
182 gpio_set_value(gpio_cfg[board_type].otgpwr_en, on);
186 #endif /* CONFIG_USB_EHCI_MX6 */
188 #ifdef CONFIG_MXC_SPI
189 iomux_v3_cfg_t const ecspi1_pads[] = {
191 IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL)),
192 IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
193 IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
194 IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
197 int board_spi_cs_gpio(unsigned bus, unsigned cs)
199 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
202 static void setup_spi(void)
204 gpio_request(IMX_GPIO_NR(3, 19), "spi_cs");
205 gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
206 SETUP_IOMUX_PADS(ecspi1_pads);
210 /* configure eth0 PHY board-specific LED behavior */
211 int board_phy_config(struct phy_device *phydev)
216 if (phydev->phy_id == 0x1410dd1) {
218 * Page 3, Register 16: LED[2:0] Function Control Register
219 * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
220 * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
222 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
223 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
226 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
227 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
230 if (phydev->drv->config)
231 phydev->drv->config(phydev);
236 #ifdef CONFIG_MV88E61XX_SWITCH
237 int mv88e61xx_hw_reset(struct phy_device *phydev)
239 struct mii_dev *bus = phydev->bus;
241 /* GPIO[0] output, CLK125 */
242 debug("enabling RGMII_REFCLK\n");
243 bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
244 0x1a /*MV_SCRATCH_MISC*/,
245 (1 << 15) | (0x62 /*MV_GPIO_DIR*/ << 8) | 0xfe);
246 bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
247 0x1a /*MV_SCRATCH_MISC*/,
248 (1 << 15) | (0x68 /*MV_GPIO01_CNTL*/ << 8) | 7);
250 /* RGMII delay - Physical Control register bit[15:14] */
251 debug("setting port%d RGMII rx/tx delay\n", CONFIG_MV88E61XX_CPU_PORT);
252 /* forced 1000mbps full-duplex link */
253 bus->write(bus, 0x10 + CONFIG_MV88E61XX_CPU_PORT, 0, 1, 0xc0fe);
254 phydev->autoneg = AUTONEG_DISABLE;
255 phydev->speed = SPEED_1000;
256 phydev->duplex = DUPLEX_FULL;
258 /* LED configuration: 7:4-green (8=Activity) 3:0 amber (9=10Link) */
259 bus->write(bus, 0x10, 0, 0x16, 0x8089);
260 bus->write(bus, 0x11, 0, 0x16, 0x8089);
261 bus->write(bus, 0x12, 0, 0x16, 0x8089);
262 bus->write(bus, 0x13, 0, 0x16, 0x8089);
266 #endif // CONFIG_MV88E61XX_SWITCH
268 int board_eth_init(bd_t *bis)
270 #ifdef CONFIG_FEC_MXC
271 struct ventana_board_info *info = &ventana_info;
273 if (test_bit(EECONFIG_ETH0, info->config)) {
274 setup_iomux_enet(GP_PHY_RST);
280 e1000_initialize(bis);
284 /* For otg ethernet*/
285 usb_eth_initialize(bis);
288 /* default to the first detected enet dev */
289 if (!getenv("ethprime")) {
290 struct eth_device *dev = eth_get_dev_by_index(0);
292 setenv("ethprime", dev->name);
293 printf("set ethprime to %s\n", getenv("ethprime"));
300 #if defined(CONFIG_VIDEO_IPUV3)
302 static void enable_hdmi(struct display_info_t const *dev)
304 imx_enable_hdmi_phy();
307 static int detect_i2c(struct display_info_t const *dev)
309 return i2c_set_bus_num(dev->bus) == 0 &&
310 i2c_probe(dev->addr) == 0;
313 static void enable_lvds(struct display_info_t const *dev)
315 struct iomuxc *iomux = (struct iomuxc *)
318 /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
319 u32 reg = readl(&iomux->gpr[2]);
320 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
321 writel(reg, &iomux->gpr[2]);
323 /* Enable Backlight */
324 gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
325 gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
326 gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
327 SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
328 gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
331 struct display_info_t const displays[] = {{
335 .pixfmt = IPU_PIX_FMT_RGB24,
336 .detect = detect_hdmi,
337 .enable = enable_hdmi,
351 .vmode = FB_VMODE_NONINTERLACED
353 /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
356 .pixfmt = IPU_PIX_FMT_LVDS666,
357 .detect = detect_i2c,
358 .enable = enable_lvds,
360 .name = "Hannstar-XGA",
372 .vmode = FB_VMODE_NONINTERLACED
378 .enable = enable_lvds,
379 .pixfmt = IPU_PIX_FMT_LVDS666,
381 .name = "DLC700JMGT4",
383 .xres = 1024, /* 1024x600active pixels */
385 .pixclock = 15385, /* 64MHz */
393 .vmode = FB_VMODE_NONINTERLACED
399 .enable = enable_lvds,
400 .pixfmt = IPU_PIX_FMT_LVDS666,
402 .name = "DLC800FIGT3",
404 .xres = 1024, /* 1024x768 active pixels */
406 .pixclock = 15385, /* 64MHz */
414 .vmode = FB_VMODE_NONINTERLACED
416 size_t display_count = ARRAY_SIZE(displays);
418 static void setup_display(void)
420 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
421 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
426 /* Turn on LDB0,IPU,IPU DI0 clocks */
427 reg = __raw_readl(&mxc_ccm->CCGR3);
428 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
429 writel(reg, &mxc_ccm->CCGR3);
431 /* set LDB0, LDB1 clk select to 011/011 */
432 reg = readl(&mxc_ccm->cs2cdr);
433 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
434 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
435 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
436 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
437 writel(reg, &mxc_ccm->cs2cdr);
439 reg = readl(&mxc_ccm->cscmr2);
440 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
441 writel(reg, &mxc_ccm->cscmr2);
443 reg = readl(&mxc_ccm->chsccdr);
444 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
445 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
446 writel(reg, &mxc_ccm->chsccdr);
448 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
449 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
450 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
451 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
452 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
453 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
454 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
455 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
456 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
457 writel(reg, &iomux->gpr[2]);
459 reg = readl(&iomux->gpr[3]);
460 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
461 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
462 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
463 writel(reg, &iomux->gpr[3]);
465 /* LVDS Backlight GPIO on LVDS connector - output low */
466 SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
467 gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
469 #endif /* CONFIG_VIDEO_IPUV3 */
471 /* setup board specific PMIC */
472 int power_init_board(void)
478 #if defined(CONFIG_CMD_PCI)
479 int imx6_pcie_toggle_reset(void)
481 if (board_type < GW_UNKNOWN) {
482 uint pin = gpio_cfg[board_type].pcie_rst;
483 gpio_request(pin, "pci_rst#");
484 gpio_direction_output(pin, 0);
486 gpio_direction_output(pin, 1);
492 * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
493 * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
494 * properly and assert reset for 100ms.
496 #define MAX_PCI_DEVS 32
499 unsigned short vendor;
500 unsigned short device;
501 unsigned short class;
502 unsigned short busno; /* subbordinate busno */
503 struct pci_dev *ppar;
505 struct pci_dev pci_devs[MAX_PCI_DEVS];
509 void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
510 unsigned short vendor, unsigned short device,
511 unsigned short class)
515 struct pci_dev *pdev = &pci_devs[pci_devno++];
517 debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
518 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
520 /* store array of devs for later use in device-tree fixup */
522 pdev->vendor = vendor;
523 pdev->device = device;
526 if (class == PCI_CLASS_BRIDGE_PCI)
527 pdev->busno = ++pci_bridgeno;
531 /* fixup RC - it should be 00:00.0 not 00:01.0 */
532 if (PCI_BUS(dev) == 0)
535 /* find dev's parent */
536 for (i = 0; i < pci_devno; i++) {
537 if (pci_devs[i].busno == PCI_BUS(pdev->devfn)) {
538 pdev->ppar = &pci_devs[i];
543 /* assert downstream PERST# */
544 if (vendor == PCI_VENDOR_ID_PLX &&
545 (device & 0xfff0) == 0x8600 &&
546 PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
547 debug("configuring PLX 860X downstream PERST#\n");
548 pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
549 dw |= 0xaaa8; /* GPIO1-7 outputs */
550 pci_hose_write_config_dword(hose, dev, 0x62c, dw);
552 pci_hose_read_config_dword(hose, dev, 0x644, &dw);
553 dw |= 0xfe; /* GPIO1-7 output high */
554 pci_hose_write_config_dword(hose, dev, 0x644, dw);
559 #endif /* CONFIG_CMD_PCI */
561 #ifdef CONFIG_SERIAL_TAG
563 * called when setting up ATAGS before booting kernel
564 * populate serialnum from the following (in order of priority):
568 void get_board_serial(struct tag_serialnr *serialnr)
570 char *serial = getenv("serial#");
574 serialnr->low = simple_strtoul(serial, NULL, 10);
575 } else if (ventana_info.model[0]) {
577 serialnr->low = ventana_info.serial;
589 int board_early_init_f(void)
593 #if defined(CONFIG_VIDEO_IPUV3)
601 gd->ram_size = imx_ddr_size();
607 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
609 clrsetbits_le32(&iomuxc_regs->gpr[1],
610 IOMUXC_GPR1_OTG_ID_MASK,
611 IOMUXC_GPR1_OTG_ID_GPIO1);
613 /* address of linux boot parameters */
614 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
616 #ifdef CONFIG_CMD_NAND
619 #ifdef CONFIG_MXC_SPI
624 #ifdef CONFIG_CMD_SATA
627 /* read Gateworks EEPROM into global struct (used later) */
628 board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
630 setup_iomux_gpio(board_type, &ventana_info);
635 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
637 * called during late init (after relocation and after board_init())
638 * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
643 struct ventana_board_info *info = &ventana_info;
644 unsigned char buf[4];
646 int quiet; /* Quiet or minimal output mode */
651 quiet = simple_strtol(p, NULL, 10);
653 setenv("quiet", "0");
655 puts("\nGateworks Corporation Copyright 2014\n");
656 if (info->model[0]) {
657 printf("Model: %s\n", info->model);
658 printf("MFGDate: %02x-%02x-%02x%02x\n",
659 info->mfgdate[0], info->mfgdate[1],
660 info->mfgdate[2], info->mfgdate[3]);
661 printf("Serial:%d\n", info->serial);
663 puts("Invalid EEPROM - board will not function fully\n");
668 /* Display GSC firmware revision/CRC/status */
672 if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
674 buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
681 #ifdef CONFIG_CMD_BMODE
683 * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
684 * see Table 8-11 and Table 5-9
685 * BOOT_CFG1[7] = 1 (boot from NAND)
686 * BOOT_CFG1[5] = 0 - raw NAND
687 * BOOT_CFG1[4] = 0 - default pad settings
688 * BOOT_CFG1[3:2] = 00 - devices = 1
689 * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
690 * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
691 * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
692 * BOOT_CFG2[0] = 0 - Reset time 12ms
694 static const struct boot_mode board_boot_modes[] = {
695 /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
696 { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
702 int misc_init_r(void)
704 struct ventana_board_info *info = &ventana_info;
708 /* set env vars based on EEPROM data */
709 if (ventana_info.model[0]) {
710 char str[16], fdt[36];
712 const char *cputype = "";
715 * FDT name will be prefixed with CPU type. Three versions
716 * will be created each increasingly generic and bootloader
717 * env scripts will try loading each from most specific to
720 if (is_cpu_type(MXC_CPU_MX6Q) ||
721 is_cpu_type(MXC_CPU_MX6D))
723 else if (is_cpu_type(MXC_CPU_MX6DL) ||
724 is_cpu_type(MXC_CPU_MX6SOLO))
726 setenv("soctype", cputype);
727 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
728 setenv("flash_layout", "large");
730 setenv("flash_layout", "normal");
731 memset(str, 0, sizeof(str));
732 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
733 str[i] = tolower(info->model[i]);
734 setenv("model", str);
735 if (!getenv("fdt_file")) {
736 sprintf(fdt, "%s-%s.dtb", cputype, str);
737 setenv("fdt_file", fdt);
739 p = strchr(str, '-');
743 setenv("model_base", str);
744 sprintf(fdt, "%s-%s.dtb", cputype, str);
745 setenv("fdt_file1", fdt);
746 if (board_type != GW551x &&
747 board_type != GW552x &&
748 board_type != GW553x)
752 sprintf(fdt, "%s-%s.dtb", cputype, str);
753 setenv("fdt_file2", fdt);
756 /* initialize env from EEPROM */
757 if (test_bit(EECONFIG_ETH0, info->config) &&
758 !getenv("ethaddr")) {
759 eth_setenv_enetaddr("ethaddr", info->mac0);
761 if (test_bit(EECONFIG_ETH1, info->config) &&
762 !getenv("eth1addr")) {
763 eth_setenv_enetaddr("eth1addr", info->mac1);
766 /* board serial-number */
767 sprintf(str, "%6d", info->serial);
768 setenv("serial#", str);
771 sprintf(str, "%d", (int) (gd->ram_size >> 20));
772 setenv("mem_mb", str);
775 /* Set a non-initialized hwconfig based on board configuration */
776 if (!strcmp(getenv("hwconfig"), "_UNKNOWN_")) {
778 if (gpio_cfg[board_type].rs232_en)
779 strcat(buf, "rs232;");
780 for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
782 sprintf(buf1, "dio%d:mode=gpio;", i);
783 if (strlen(buf) + strlen(buf1) < sizeof(buf))
786 setenv("hwconfig", buf);
789 /* setup baseboard specific GPIO based on board and env */
790 setup_board_gpio(board_type, info);
792 #ifdef CONFIG_CMD_BMODE
793 add_board_boot_modes(board_boot_modes);
796 /* disable boot watchdog */
797 gsc_boot_wd_disable();
802 #ifdef CONFIG_OF_BOARD_SETUP
804 static int ft_sethdmiinfmt(void *blob, char *mode)
811 off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
815 if (0 == strcasecmp(mode, "yuv422bt656")) {
816 u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
819 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
820 fdt_setprop_u32(blob, off, "vidout_trc", 1);
821 fdt_setprop_u32(blob, off, "vidout_blc", 1);
822 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
823 printf(" set HDMI input mode to %s\n", mode);
824 } else if (0 == strcasecmp(mode, "yuv422smp")) {
825 u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
828 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
829 fdt_setprop_u32(blob, off, "vidout_trc", 0);
830 fdt_setprop_u32(blob, off, "vidout_blc", 0);
831 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
832 printf(" set HDMI input mode to %s\n", mode);
840 /* enable a property of a node if the node is found */
841 static inline void ft_enable_path(void *blob, const char *path)
843 int i = fdt_path_offset(blob, path);
845 debug("enabling %s\n", path);
846 fdt_status_okay(blob, i);
850 /* remove a property of a node if the node is found */
851 static inline void ft_delprop_path(void *blob, const char *path,
854 int i = fdt_path_offset(blob, path);
856 debug("removing %s/%s\n", path, name);
857 fdt_delprop(blob, i, name);
861 #if defined(CONFIG_CMD_PCI)
862 #define PCI_ID(x) ( \
863 (PCI_BUS(x->devfn)<<16)| \
864 (PCI_DEV(x->devfn)<<11)| \
865 (PCI_FUNC(x->devfn)<<8) \
867 #define PCIE_PATH "/soc/pcie@0x01000000"
868 int fdt_add_pci_node(void *blob, int par, struct pci_dev *dev)
874 sprintf(node, "pcie@%d,%d,%d", PCI_BUS(dev->devfn),
875 PCI_DEV(dev->devfn), PCI_FUNC(dev->devfn));
877 np = fdt_subnode_offset(blob, par, node);
880 np = fdt_add_subnode(blob, par, node);
882 printf(" %s failed: no space\n", __func__);
886 memset(reg, 0, sizeof(reg));
887 reg[0] = cpu_to_fdt32(PCI_ID(dev));
888 fdt_setprop(blob, np, "reg", reg, sizeof(reg));
893 /* build a path of nested PCI devs for all bridges passed through */
894 int fdt_add_pci_path(void *blob, struct pci_dev *dev)
896 struct pci_dev *bridges[MAX_PCI_DEVS];
899 /* build list of parents */
900 np = fdt_path_offset(blob, PCIE_PATH);
910 /* now add them the to DT in reverse order */
912 np = fdt_add_pci_node(blob, np, bridges[k]);
921 * The GW16082 has a hardware errata errata such that it's
922 * INTA/B/C/D are mis-mapped to its four slots (slot12-15). Because
923 * of this normal PCI interrupt swizzling will not work so we will
924 * provide an irq-map via device-tree.
926 int fdt_fixup_gw16082(void *blob, int np, struct pci_dev *dev)
930 uint32_t imap_new[8*4*4];
931 const uint32_t *imap;
936 /* build irq-map based on host controllers map */
937 host = fdt_path_offset(blob, PCIE_PATH);
939 printf(" %s failed: missing host\n", __func__);
943 /* use interrupt data from root complex's node */
944 imap = fdt_getprop(blob, host, "interrupt-map", &len);
945 if (!imap || len != 128) {
946 printf(" %s failed: invalid interrupt-map\n",
948 return -FDT_ERR_NOTFOUND;
951 /* obtain irq's of host controller in pin order */
952 for (i = 0; i < 4; i++)
953 irq[(fdt32_to_cpu(imap[(i*8)+3])-1)%4] = imap[(i*8)+6];
956 * determine number of swizzles necessary:
957 * For each bridge we pass through we need to swizzle
958 * the number of the slot we are on.
964 while(d && d->ppar) {
965 b += PCI_DEV(d->devfn);
969 /* create new irq mappings for slots12-15
970 * <skt> <idsel> <slot> <skt-inta> <skt-intb>
971 * J3 AD28 12 INTD INTA
972 * J4 AD29 13 INTC INTD
973 * J5 AD30 14 INTB INTC
974 * J2 AD31 15 INTA INTB
976 for (i = 0; i < 4; i++) {
977 /* addr matches bus:dev:func */
978 u32 addr = dev->busno << 16 | (12+i) << 11;
980 /* default cells from root complex */
981 memcpy(&imap_new[i*32], imap, 128);
982 /* first cell is PCI device address (BDF) */
983 imap_new[(i*32)+(0*8)+0] = cpu_to_fdt32(addr);
984 imap_new[(i*32)+(1*8)+0] = cpu_to_fdt32(addr);
985 imap_new[(i*32)+(2*8)+0] = cpu_to_fdt32(addr);
986 imap_new[(i*32)+(3*8)+0] = cpu_to_fdt32(addr);
987 /* third cell is pin */
988 imap_new[(i*32)+(0*8)+3] = cpu_to_fdt32(1);
989 imap_new[(i*32)+(1*8)+3] = cpu_to_fdt32(2);
990 imap_new[(i*32)+(2*8)+3] = cpu_to_fdt32(3);
991 imap_new[(i*32)+(3*8)+3] = cpu_to_fdt32(4);
992 /* sixth cell is relative interrupt */
993 imap_new[(i*32)+(0*8)+6] = irq[(15-(12+i)+b+0)%4];
994 imap_new[(i*32)+(1*8)+6] = irq[(15-(12+i)+b+1)%4];
995 imap_new[(i*32)+(2*8)+6] = irq[(15-(12+i)+b+2)%4];
996 imap_new[(i*32)+(3*8)+6] = irq[(15-(12+i)+b+3)%4];
998 fdt_setprop(blob, np, "interrupt-map", imap_new,
1000 reg[0] = cpu_to_fdt32(0xfff00);
1003 reg[3] = cpu_to_fdt32(0x7);
1004 fdt_setprop(blob, np, "interrupt-map-mask", reg, sizeof(reg));
1005 fdt_setprop_cell(blob, np, "#interrupt-cells", 1);
1006 fdt_setprop_string(blob, np, "device_type", "pci");
1007 fdt_setprop_cell(blob, np, "#address-cells", 3);
1008 fdt_setprop_cell(blob, np, "#size-cells", 2);
1009 printf(" Added custom interrupt-map for GW16082\n");
1014 /* The sky2 GigE MAC obtains it's MAC addr from device-tree by default */
1015 int fdt_fixup_sky2(void *blob, int np, struct pci_dev *dev)
1019 unsigned char mac_addr[6];
1022 sprintf(mac, "eth1addr");
1025 for (j = 0; j < 6; j++) {
1027 simple_strtoul(tmp, &end,16) : 0;
1029 tmp = (*end) ? end+1 : end;
1031 fdt_setprop(blob, np, "local-mac-address", mac_addr,
1033 printf(" Added mac addr for eth1\n");
1041 * PCI DT nodes must be nested therefore if we need to apply a DT fixup
1042 * we will walk the PCI bus and add bridge nodes up to the device receiving
1045 void ft_board_pci_fixup(void *blob, bd_t *bd)
1048 struct pci_dev *dev;
1050 for (i = 0; i < pci_devno; i++) {
1054 * The GW16082 consists of a TI XIO2001 PCIe-to-PCI bridge and
1055 * an EEPROM at i2c1-0x50.
1057 if ((dev->vendor == PCI_VENDOR_ID_TI) &&
1058 (dev->device == 0x8240) &&
1059 (i2c_set_bus_num(1) == 0) &&
1060 (i2c_probe(0x50) == 0))
1062 np = fdt_add_pci_path(blob, dev);
1064 fdt_fixup_gw16082(blob, np, dev);
1067 /* ethernet1 mac address */
1068 else if ((dev->vendor == PCI_VENDOR_ID_MARVELL) &&
1069 (dev->device == 0x4380))
1071 np = fdt_add_pci_path(blob, dev);
1073 fdt_fixup_sky2(blob, np, dev);
1077 #endif /* if defined(CONFIG_CMD_PCI) */
1080 * called prior to booting kernel or by 'fdt boardsetup' command
1082 * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1083 * - mtd partitions based on mtdparts/mtdids env
1084 * - system-serial (board serial num from EEPROM)
1085 * - board (full model from EEPROM)
1086 * - peripherals removed from DTB if not loaded on board (per EEPROM config)
1088 #define UART1_PATH "/soc/aips-bus@02100000/serial@021ec000"
1089 #define WDOG1_PATH "/soc/aips-bus@02000000/wdog@020bc000"
1090 #define WDOG2_PATH "/soc/aips-bus@02000000/wdog@020c0000"
1091 #define GPIO3_PATH "/soc/aips-bus@02000000/gpio@020a4000"
1092 int ft_board_setup(void *blob, bd_t *bd)
1094 struct ventana_board_info *info = &ventana_info;
1095 struct ventana_eeprom_config *cfg;
1096 struct node_info nodes[] = {
1097 { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */
1098 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
1100 const char *model = getenv("model");
1101 const char *display = getenv("display");
1105 /* determine board revision */
1106 for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
1107 if (ventana_info.model[i] >= 'A') {
1108 rev = ventana_info.model[i];
1113 if (getenv("fdt_noauto")) {
1114 puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
1118 if (test_bit(EECONFIG_NAND, info->config)) {
1119 /* Update partition nodes using info from mtdparts env var */
1120 puts(" Updating MTD partitions...\n");
1121 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1124 /* Update display timings from display env var */
1126 if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
1128 printf(" Set display timings for %s...\n", display);
1131 printf(" Adjusting FDT per EEPROM for %s...\n", model);
1133 /* board serial number */
1134 fdt_setprop(blob, 0, "system-serial", getenv("serial#"),
1135 strlen(getenv("serial#")) + 1);
1137 /* board (model contains model from device-tree) */
1138 fdt_setprop(blob, 0, "board", info->model,
1139 strlen((const char *)info->model) + 1);
1141 /* set desired digital video capture format */
1142 ft_sethdmiinfmt(blob, getenv("hdmiinfmt"));
1145 * Board model specific fixups
1147 switch (board_type) {
1150 * disable wdog node for GW51xx-A/B to work around
1151 * errata causing wdog timer to be unreliable.
1153 if (rev >= 'A' && rev < 'C') {
1154 i = fdt_path_offset(blob, WDOG1_PATH);
1156 fdt_status_disabled(blob, i);
1159 /* GW51xx-E adds WDOG1_B external reset */
1161 ft_delprop_path(blob, WDOG1_PATH,
1162 "fsl,ext-reset-output");
1166 /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
1167 if (info->model[4] == '2') {
1171 i = fdt_node_offset_by_compatible(blob, -1,
1174 range = (u32 *)fdt_getprop(blob, i,
1175 "reset-gpio", NULL);
1178 i = fdt_path_offset(blob, GPIO3_PATH);
1180 handle = fdt_get_phandle(blob, i);
1182 range[0] = cpu_to_fdt32(handle);
1183 range[1] = cpu_to_fdt32(23);
1187 /* these have broken usd_vsel */
1188 if (strstr((const char *)info->model, "SP318-B") ||
1189 strstr((const char *)info->model, "SP331-B"))
1190 gpio_cfg[board_type].usd_vsel = 0;
1192 /* GW520x-E adds WDOG1_B external reset */
1193 if (info->model[4] == '0' && rev < 'E')
1194 ft_delprop_path(blob, WDOG1_PATH,
1195 "fsl,ext-reset-output");
1197 /* GW522x-B adds WDOG1_B external reset */
1198 if (info->model[4] == '2' && rev < 'B')
1199 ft_delprop_path(blob, WDOG1_PATH,
1200 "fsl,ext-reset-output");
1205 /* GW53xx-E adds WDOG1_B external reset */
1207 ft_delprop_path(blob, WDOG1_PATH,
1208 "fsl,ext-reset-output");
1213 * disable serial2 node for GW54xx for compatibility with older
1214 * 3.10.x kernel that improperly had this node enabled in the DT
1216 i = fdt_path_offset(blob, UART1_PATH);
1218 fdt_del_node(blob, i);
1220 /* GW54xx-E adds WDOG2_B external reset */
1222 ft_delprop_path(blob, WDOG2_PATH,
1223 "fsl,ext-reset-output");
1228 * isolate CSI0_DATA_EN for GW551x-A to work around errata
1229 * causing non functional digital video in (it is not hooked up)
1234 const u32 *handle = NULL;
1236 i = fdt_node_offset_by_compatible(blob, -1,
1237 "fsl,imx-tda1997x-video");
1239 handle = fdt_getprop(blob, i, "pinctrl-0",
1242 i = fdt_node_offset_by_phandle(blob,
1243 fdt32_to_cpu(*handle));
1245 range = (u32 *)fdt_getprop(blob, i, "fsl,pins",
1249 for (i = 0; i < len; i += 6) {
1250 u32 mux_reg = fdt32_to_cpu(range[i+0]);
1251 u32 conf_reg = fdt32_to_cpu(range[i+1]);
1252 /* mux PAD_CSI0_DATA_EN to GPIO */
1253 if (is_cpu_type(MXC_CPU_MX6Q) &&
1256 range[i+3] = cpu_to_fdt32(0x5);
1257 else if (!is_cpu_type(MXC_CPU_MX6Q) &&
1260 range[i+3] = cpu_to_fdt32(0x5);
1262 fdt_setprop_inplace(blob, i, "fsl,pins", range,
1266 /* set BT656 video format */
1267 ft_sethdmiinfmt(blob, "yuv422bt656");
1270 /* GW551x-C adds WDOG1_B external reset */
1272 ft_delprop_path(blob, WDOG1_PATH,
1273 "fsl,ext-reset-output");
1278 for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
1279 struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
1282 sprintf(arg, "dio%d", i);
1285 if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
1288 sprintf(path, "/soc/aips-bus@02000000/pwm@%08x",
1289 0x02080000 + (0x4000 * (cfg->pwm_param - 1)));
1290 printf(" Enabling pwm%d for DIO%d\n",
1292 ft_enable_path(blob, path);
1296 /* remove no-1-8-v if UHS-I support is present */
1297 if (gpio_cfg[board_type].usd_vsel) {
1298 debug("Enabling UHS-I support\n");
1299 ft_delprop_path(blob, "/soc/aips-bus@02100000/usdhc@02198000",
1303 #if defined(CONFIG_CMD_PCI)
1304 if (!getenv("nopcifixup"))
1305 ft_board_pci_fixup(blob, bd);
1309 * Peripheral Config:
1310 * remove nodes by alias path if EEPROM config tells us the
1311 * peripheral is not loaded on the board.
1313 if (getenv("fdt_noconfig")) {
1314 puts(" Skiping periperhal config (fdt_noconfig defined)\n");
1319 if (!test_bit(cfg->bit, info->config)) {
1320 fdt_del_node_and_alias(blob, cfg->dtalias ?
1321 cfg->dtalias : cfg->name);
1328 #endif /* CONFIG_OF_BOARD_SETUP */
1330 static struct mxc_serial_platdata ventana_mxc_serial_plat = {
1331 .reg = (struct mxc_uart *)UART2_BASE,
1334 U_BOOT_DEVICE(ventana_serial) = {
1335 .name = "serial_mxc",
1336 .platdata = &ventana_mxc_serial_plat,