1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2013 Gateworks Corporation
5 * Author: Tim Harvey <tharvey@gateworks.com>
10 /* i2c slave addresses */
11 #define GSC_SC_ADDR 0x20
12 #define GSC_RTC_ADDR 0x68
13 #define GSC_HWMON_ADDR 0x29
14 #define GSC_EEPROM_ADDR 0x51
16 /* System Controller registers */
25 /* System Controller Control1 bits */
27 GSC_SC_CTRL1_WDTIME = 4, /* 1 = 60s timeout, 0 = 30s timeout */
28 GSC_SC_CTRL1_WDEN = 5, /* 1 = enable, 0 = disable */
29 GSC_SC_CTRL1_WDDIS = 7, /* 1 = disable boot watchdog */
32 /* System Controller Interrupt bits */
34 GSC_SC_IRQ_PB = 0, /* Pushbutton switch */
35 GSC_SC_IRQ_SECURE = 1, /* Secure Key erase operation complete */
36 GSC_SC_IRQ_EEPROM_WP = 2, /* EEPROM write violation */
37 GSC_SC_IRQ_GPIO = 4, /* GPIO change */
38 GSC_SC_IRQ_TAMPER = 5, /* Tamper detect */
39 GSC_SC_IRQ_WATCHDOG = 6, /* Watchdog trip */
40 GSC_SC_IRQ_PBLONG = 7, /* Pushbutton long hold */
43 /* Hardware Monitor registers */
45 GSC_HWMON_TEMP = 0x00,
47 GSC_HWMON_VDD_3P3 = 0x05,
48 GSC_HWMON_VBATT = 0x08,
49 GSC_HWMON_VDD_5P0 = 0x0b,
50 GSC_HWMON_VDD_CORE = 0x0e,
51 GSC_HWMON_VDD_HIGH = 0x14,
52 GSC_HWMON_VDD_DDR = 0x17,
53 GSC_HWMON_VDD_SOC = 0x11,
54 GSC_HWMON_VDD_1P8 = 0x1d,
55 GSC_HWMON_VDD_IO2 = 0x20,
56 GSC_HWMON_VDD_2P5 = 0x23,
57 GSC_HWMON_VDD_IO3 = 0x26,
58 GSC_HWMON_VDD_IO4 = 0x29,
62 * I2C transactions to the GSC are done via these functions which
63 * perform retries in the case of a busy GSC NAK'ing the transaction
65 int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len);
66 int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len);
67 int gsc_info(int verbose);
68 int gsc_boot_wd_disable(void);