1 #ifndef __MINI2440_BOARD_CONF_H__
2 #define __MINI2440_BOARD_CONF_H__
21 #define B1_BWSCON (DW32)
22 #define B2_BWSCON (DW16)
23 #define B3_BWSCON (DW16 + WAIT + UBLB)
24 #define B4_BWSCON (DW16 + WAIT + UBLB)
25 #define B5_BWSCON (DW16)
26 #define B6_BWSCON (DW32)
27 #define B7_BWSCON (DW32)
32 #define B0_Tacs 0x0 /* 0clk */
33 #define B0_Tcos 0x0 /* 0clk */
34 #define B0_Tacc 0x7 /* 14clk */
35 #define B0_Tcoh 0x0 /* 0clk */
36 #define B0_Tah 0x0 /* 0clk */
37 #define B0_Tacp 0x0 /* 0clk */
38 #define B0_PMC 0x0 /* normal */
57 #define B3_Tcos 0x3 /* 4clk */
59 #define B3_Tcoh 0x1 /* 1clk */
60 #define B3_Tah 0x3 /* 4clk */
83 #define SDRAM_MT 0x3 /* SDRAM */
84 #define SDRAM_Trcd 0x0 /* 2clk */
85 #define SDRAM_SCAN_9 0x1 /* 9bit */
86 #define SDRAM_SCAN_10 0x2 /* 10bit */
88 #define SDRAM_64MB ((SDRAM_MT<<15) + (SDRAM_Trcd<<2) + (SDRAM_SCAN_9))
93 #define REFEN 0x1 /* Refresh enable */
94 #define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
95 #define Trp 0x1 /* 3clk */
96 #define Trc 0x3 /* 7clk */
97 #define Tchr 0x0 /* unused */
98 #define REFCNT 1012 /* period=10.37us, HCLK=100Mhz, (2048 + 1-10.37*100) */
105 #define CL 0x3 /* 3 clocks */
112 #define BK76MAP 0x2 /* 128MB/128MB */
113 #define SCLK_EN 0x1 /* SCLK active */
114 #define SCKE_EN 0x1 /* SDRAM power down mode enable */
115 #define BURST_EN 0x1 /* Burst enable */
120 #define BANK_CONF ((0 + (B1_BWSCON<<4) + (B2_BWSCON<<8) + (B3_BWSCON<<12) + \
121 (B4_BWSCON<<16) + (B5_BWSCON<<20) + (B6_BWSCON<<24) + \
124 #define B0_CONF ((B0_Tacs<<13) + (B0_Tcos<<11) + (B0_Tacc<<8) + \
125 (B0_Tcoh<<6) + (B0_Tah<<4) + (B0_Tacp<<2) + (B0_PMC))
126 #define B1_CONF ((B1_Tacs<<13) + (B1_Tcos<<11) + (B1_Tacc<<8) + \
127 (B1_Tcoh<<6) + (B1_Tah<<4) + (B1_Tacp<<2) + (B1_PMC))
128 #define B2_CONF ((B2_Tacs<<13) + (B2_Tcos<<11) + (B2_Tacc<<8) + \
129 (B2_Tcoh<<6) + (B2_Tah<<4) + (B2_Tacp<<2) + (B2_PMC))
130 #define B3_CONF ((B3_Tacs<<13) + (B3_Tcos<<11) + (B3_Tacc<<8) + \
131 (B3_Tcoh<<6) + (B3_Tah<<4) + (B3_Tacp<<2) + (B3_PMC))
132 #define B4_CONF ((B4_Tacs<<13) + (B4_Tcos<<11) + (B4_Tacc<<8) + \
133 (B4_Tcoh<<6) + (B4_Tah<<4) + (B4_Tacp<<2) + (B4_PMC))
134 #define B5_CONF ((B5_Tacs<<13) + (B5_Tcos<<11) + (B5_Tacc<<8) + \
135 (B5_Tcoh<<6) + (B5_Tah<<4) + (B5_Tacp<<2) + (B5_PMC))
137 #define MEM_TIMING (REFEN<<23) + (TREFMD<<22) + (Trp<<20) + \
138 (Trc<<18) + (Tchr<<16) + REFCNT
140 #define BANKSIZE_CONF (BK76MAP) + (SCLK_EN<<4) + (SCKE_EN<<5) + (BURST_EN<<7)
141 #define B6_MRSR (CL<<4)
142 #define B7_MRSR (CL<<4)