3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
10 * Michel Pollet <buserror@gmail.com>
13 * Gabriel Huau <contact@huau-gabriel.fr>
15 * See file CREDITS for list of people who contributed to this
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
35 #include <asm/arch/s3c2440.h>
36 #include <asm/arch/iomux.h>
37 #include <asm/arch/gpio.h>
43 DECLARE_GLOBAL_DATA_PTR;
45 static inline void pll_delay(unsigned long loops)
47 __asm__ volatile ("1:\n"
49 "bne 1b" : "=r" (loops) : "0" (loops));
52 int board_early_init_f(void)
54 struct s3c24x0_clock_power * const clk_power =
55 s3c24x0_get_base_clock_power();
57 /* to reduce PLL lock time, adjust the LOCKTIME register */
58 clk_power->locktime = 0xFFFFFF; /* Max PLL Lock time count */
59 clk_power->clkdivn = CLKDIVN_VAL;
62 clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
63 /* some delay between MPLL and UPLL */
67 clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
69 /* some delay between MPLL and UPLL */
76 * Miscellaneous platform dependent initialisations
80 struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
82 /* IOMUX Port H : UART Configuration */
83 gpio->gphcon = IOMUXH_nCTS0 | IOMUXH_nRTS0 | IOMUXH_TXD0 | IOMUXH_RXD0 |
84 IOMUXH_TXD1 | IOMUXH_RXD1 | IOMUXH_TXD2 | IOMUXH_RXD2;
86 gpio_direction_output(GPH8, 0);
87 gpio_direction_output(GPH9, 0);
88 gpio_direction_output(GPH10, 0);
90 /* adress of boot parameters */
91 gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR;
98 struct s3c24x0_memctl *memctl = s3c24x0_get_base_memctl();
101 * Configuring bus width and timing
102 * Initialize clocks for each bank 0..5
103 * Bank 3 and 4 are used for DM9000
105 writel(BANK_CONF, &memctl->bwscon);
106 writel(B0_CONF, &memctl->bankcon[0]);
107 writel(B1_CONF, &memctl->bankcon[1]);
108 writel(B2_CONF, &memctl->bankcon[2]);
109 writel(B3_CONF, &memctl->bankcon[3]);
110 writel(B4_CONF, &memctl->bankcon[4]);
111 writel(B5_CONF, &memctl->bankcon[5]);
113 /* Bank 6 and 7 are used for DRAM */
114 writel(SDRAM_64MB, &memctl->bankcon[6]);
115 writel(SDRAM_64MB, &memctl->bankcon[7]);
117 writel(MEM_TIMING, &memctl->refresh);
118 writel(BANKSIZE_CONF, &memctl->banksize);
119 writel(B6_MRSR, &memctl->mrsrb6);
120 writel(B7_MRSR, &memctl->mrsrb7);
122 gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
127 int board_eth_init(bd_t *bis)
129 #ifdef CONFIG_DRIVER_DM9000
130 return dm9000_initialize(bis);