1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014 Freescale Semiconductor, Inc.
10 #include <fdt_support.h>
15 #include <asm/global_data.h>
16 #include <linux/compiler.h>
18 #include <asm/processor.h>
19 #include <asm/cache.h>
20 #include <asm/immap_85xx.h>
21 #include <asm/fsl_law.h>
22 #include <asm/fsl_serdes.h>
23 #include <asm/fsl_liodn.h>
24 #include <clock_legacy.h>
29 #include "../common/vid.h"
31 DECLARE_GLOBAL_DATA_PTR;
33 #if CONFIG_IS_ENABLED(DM_SERIAL)
34 int get_serial_clock(void)
36 return get_bus_freq(0) / 2;
42 struct cpu_type *cpu = gd->arch.cpu;
45 printf("Board: %sRDB, ", cpu->name);
46 printf("Board rev: 0x%02x CPLD ver: 0x%02x%02x, ",
47 CPLD_READ(hw_ver), CPLD_READ(sw_maj_ver), CPLD_READ(sw_min_ver));
49 sw = CPLD_READ(vbank);
50 sw = sw & CPLD_BANK_SEL_MASK;
53 printf("vBank: %d\n", sw);
55 printf("Unsupported Bank=%x\n", sw);
57 puts("SERDES Reference Clocks:\n");
58 printf(" SERDES1=100MHz SERDES2=156.25MHz\n"
59 " SERDES3=100MHz SERDES4=100MHz\n");
64 int board_early_init_r(void)
66 const unsigned int flashbase = CFG_SYS_FLASH_BASE;
67 int flash_esel = find_tlb_idx((void *)flashbase, 1);
70 * Remap Boot flash + PROMJET region to caching-inhibited
71 * so that flash can be erased properly.
74 /* Flush d-cache and invalidate i-cache of any FLASH data */
78 if (flash_esel == -1) {
79 /* very unlikely unless something is messed up */
80 puts("Error: Could not find TLB for FLASH BASE\n");
81 flash_esel = 2; /* give our best effort to continue */
83 /* invalidate existing TLB entry for flash + promjet */
84 disable_tlb(flash_esel);
87 set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS,
88 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
89 0, flash_esel, BOOKE_PAGESZ_256M, 1);
92 * Adjust core voltage according to voltage ID
93 * This function changes I2C mux to channel 2.
96 printf("Warning: Adjusting core voltage failed.\n");
103 int misc_init_r(void)
108 int ft_board_setup(void *blob, struct bd_info *bd)
113 ft_cpu_setup(blob, bd);
115 base = env_get_bootm_low();
116 size = env_get_bootm_size();
118 fdt_fixup_memory(blob, (u64)base, (u64)size);
121 pci_of_setup(blob, bd);
124 fdt_fixup_liodn(blob);
125 fsl_fdt_fixup_dr_usb(blob, bd);
127 #ifdef CONFIG_SYS_DPAA_FMAN
128 #ifndef CONFIG_DM_ETH
129 fdt_fixup_fman_ethernet(blob);
131 fdt_fixup_board_enet(blob);
138 * This function is called by bdinfo to print detail board information.
139 * As an exmaple for future board, we organize the messages into
140 * several sections. If applicable, the message is in the format of
142 * It should aligned with normal output of bdinfo command.
144 * Voltage: Core, DDR and another configurable voltages
145 * Clock : Critical clocks which are not printed already
146 * RCW : RCW source if not printed already
147 * Misc : Other important information not in above catagories
149 void board_detail(void)
153 /* RCW section SW3[4] */
155 puts("RCW source = ");
156 switch (rcwsrc & 0x1) {
161 puts("I2C normal addressing\n");
166 ulong *cs4340_get_fw_addr(void)
168 ulong cortina_fw_addr = CONFIG_CORTINA_FW_ADDR;
170 #ifdef CONFIG_SYS_CORTINA_FW_IN_NOR
173 sw = CPLD_READ(vbank);
174 sw = sw & CPLD_BANK_SEL_MASK;
177 cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR;
179 cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR_ALTBANK;
182 return (ulong *)cortina_fw_addr;