1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2015 Freescale Semiconductor, Inc.
5 * Author: Chunhe Lan <Chunhe.Lan@freescale.com>
9 #include <clock_legacy.h>
11 #include <env_internal.h>
13 #include <asm/global_data.h>
19 #include <fsl_esdhc.h>
24 #define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
26 DECLARE_GLOBAL_DATA_PTR;
28 phys_size_t get_effective_memsize(void)
30 return CONFIG_SYS_L3_SIZE;
33 unsigned long get_board_sys_clk(void)
35 return CONFIG_SYS_CLK_FREQ;
38 void board_init_f(ulong bootflag)
40 u32 plat_ratio, sys_clk, ccb_clk;
41 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
43 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
44 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
46 /* Update GD pointer */
47 gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
49 /* compiler optimization barrier needed for GCC >= 3.4 */
50 __asm__ __volatile__("" : : : "memory");
54 /* initialize selected port with appropriate baud rate */
55 sys_clk = get_board_sys_clk();
56 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
57 ccb_clk = sys_clk * plat_ratio / 2;
59 ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
60 ccb_clk / 16 / CONFIG_BAUDRATE);
62 puts("\nSD boot...\n");
64 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
67 void board_init_r(gd_t *gd, ulong dest_addr)
71 bd = (struct bd_info *)(gd + sizeof(gd_t));
72 memset(bd, 0, sizeof(struct bd_info));
77 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
78 CONFIG_SPL_RELOC_MALLOC_SIZE);
79 gd->flags |= GD_FLG_FULL_MALLOC_INIT;
82 mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
83 (uchar *)SPL_ENV_ADDR);
85 gd->env_addr = (ulong)(SPL_ENV_ADDR);
86 gd->env_valid = ENV_VALID;