1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2012 Freescale Semiconductor, Inc.
13 #include <linux/compiler.h>
15 #include <asm/processor.h>
16 #include <asm/cache.h>
17 #include <asm/immap_85xx.h>
18 #include <asm/fsl_law.h>
19 #include <asm/fsl_serdes.h>
20 #include <asm/fsl_liodn.h>
23 #include "../common/qixis.h"
24 #include "../common/vsc3316_3308.h"
26 #include "t4240qds_qixis.h"
28 DECLARE_GLOBAL_DATA_PTR;
30 static int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
31 {8, 8}, {9, 9}, {14, 14}, {15, 15} };
33 static int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
34 {10, 10}, {11, 11}, {12, 12}, {13, 13} };
36 static int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
37 {10, 11}, {11, 10}, {12, 2}, {13, 3} };
39 static int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
40 {8, 9}, {9, 8}, {14, 1}, {15, 0} };
46 struct cpu_type *cpu = gd->arch.cpu;
49 printf("Board: %sQDS, ", cpu->name);
50 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
51 QIXIS_READ(id), QIXIS_READ(arch));
53 sw = QIXIS_READ(brdcfg[0]);
54 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
57 printf("vBank: %d\n", sw);
63 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
65 printf("FPGA: v%d (%s), build %d",
66 (int)QIXIS_READ(scver), qixis_read_tag(buf),
67 (int)qixis_read_minor());
68 /* the timestamp string contains "\n" at the end */
69 printf(" on %s", qixis_read_time(buf));
72 * Display the actual SERDES reference clocks as configured by the
73 * dip switches on the board. Note that the SWx registers could
74 * technically be set to force the reference clocks to match the
75 * values that the SERDES expects (or vice versa). For now, however,
76 * we just display both values and hope the user notices when they
79 puts("SERDES Reference Clocks: ");
80 sw = QIXIS_READ(brdcfg[2]);
81 for (i = 0; i < MAX_SERDES; i++) {
82 static const char * const freq[] = {
83 "100", "125", "156.25", "161.1328125"};
84 unsigned int clock = (sw >> (6 - 2 * i)) & 3;
86 printf("SERDES%u=%sMHz ", i+1, freq[clock]);
93 int select_i2c_ch_pca9547(u8 ch)
97 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
99 puts("PCA: failed to select proper channel\n");
107 * read_voltage from sensor on I2C bus
108 * We use average of 4 readings, waiting for 532us befor another reading
110 #define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */
111 #define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */
113 static inline int read_voltage(void)
115 int i, ret, voltage_read = 0;
118 for (i = 0; i < NUM_READINGS; i++) {
119 ret = i2c_read(I2C_VOL_MONITOR_ADDR,
120 I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
122 printf("VID: failed to read core voltage\n");
125 if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
126 printf("VID: Core voltage sensor error\n");
129 debug("VID: bus voltage reads 0x%04x\n", vol_mon);
131 voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
132 udelay(WAIT_FOR_ADC);
134 /* calculate the average */
135 voltage_read /= NUM_READINGS;
141 * We need to calculate how long before the voltage starts to drop or increase
142 * It returns with the loop count. Each loop takes several readings (532us)
144 static inline int wait_for_voltage_change(int vdd_last)
146 int timeout, vdd_current;
148 vdd_current = read_voltage();
149 /* wait until voltage starts to drop */
150 for (timeout = 0; abs(vdd_last - vdd_current) <= 4 &&
151 timeout < 100; timeout++) {
152 vdd_current = read_voltage();
154 if (timeout >= 100) {
155 printf("VID: Voltage adjustment timeout\n");
162 * argument 'wait' is the time we know the voltage difference can be measured
163 * this function keeps reading the voltage until it is stable
165 static inline int wait_for_voltage_stable(int wait)
167 int timeout, vdd_current, vdd_last;
169 vdd_last = read_voltage();
170 udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
171 /* wait until voltage is stable */
172 vdd_current = read_voltage();
173 for (timeout = 0; abs(vdd_last - vdd_current) >= 4 &&
174 timeout < 100; timeout++) {
175 vdd_last = vdd_current;
176 udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
177 vdd_current = read_voltage();
179 if (timeout >= 100) {
180 printf("VID: Voltage adjustment timeout\n");
187 static inline int set_voltage(u8 vid)
191 vdd_last = read_voltage();
192 QIXIS_WRITE(brdcfg[6], vid);
193 wait = wait_for_voltage_change(vdd_last);
196 debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC);
197 wait = wait ? wait : 1;
199 vdd_last = wait_for_voltage_stable(wait);
202 debug("VID: Current voltage is %d mV\n", vdd_last);
208 static int adjust_vdd(ulong vdd_override)
210 int re_enable = disable_interrupts();
211 ccsr_gur_t __iomem *gur =
212 (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
215 int vdd_target, vdd_current, vdd_last;
217 unsigned long vdd_string_override;
219 static const uint16_t vdd[32] = {
252 ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR);
254 debug("VID: I2c failed to switch channel\n");
259 /* get the voltage ID from fuse status register */
260 fusesr = in_be32(&gur->dcfg_fusesr);
261 vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
262 FSL_CORENET_DCFG_FUSESR_VID_MASK;
263 if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) {
264 vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
265 FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
267 vdd_target = vdd[vid];
269 /* check override variable for overriding VDD */
270 vdd_string = env_get("t4240qds_vdd_mv");
271 if (vdd_override == 0 && vdd_string &&
272 !strict_strtoul(vdd_string, 10, &vdd_string_override))
273 vdd_override = vdd_string_override;
274 if (vdd_override >= 819 && vdd_override <= 1212) {
275 vdd_target = vdd_override * 10; /* convert to 1/10 mV */
276 debug("VDD override is %lu\n", vdd_override);
277 } else if (vdd_override != 0) {
278 printf("Invalid value.\n");
281 if (vdd_target == 0) {
282 debug("VID: VID not used\n");
286 /* round up and divice by 10 to get a value in mV */
287 vdd_target = DIV_ROUND_UP(vdd_target, 10);
288 debug("VID: vid = %d mV\n", vdd_target);
292 * Check current board VID setting
293 * Voltage regulator support output to 6.250mv step
294 * The highes voltage allowed for this board is (vid=0x40) 1.21250V
295 * the lowest is (vid=0x7f) 0.81875V
297 vid_current = QIXIS_READ(brdcfg[6]);
298 vdd_current = 121250 - (vid_current - 0x40) * 625;
299 debug("VID: Current vid setting is (0x%x) %d mV\n",
300 vid_current, vdd_current/100);
303 * Read voltage monitor to check real voltage.
304 * Voltage monitor LSB is 4mv.
306 vdd_last = read_voltage();
308 printf("VID: Could not read voltage sensor abort VID adjustment\n");
312 debug("VID: Core voltage is at %d mV\n", vdd_last);
314 * Adjust voltage to at or 8mV above target.
315 * Each step of adjustment is 6.25mV.
316 * Stepping down too fast may cause over current.
318 while (vdd_last > 0 && vid_current < 0x80 &&
319 vdd_last > (vdd_target + 8)) {
321 vdd_last = set_voltage(vid_current);
324 * Check if we need to step up
325 * This happens when board voltage switch was set too low
327 while (vdd_last > 0 && vid_current >= 0x40 &&
328 vdd_last < vdd_target + 2) {
330 vdd_last = set_voltage(vid_current);
333 printf("VID: Core voltage %d mV\n", vdd_last);
343 /* Configure Crossbar switches for Front-Side SerDes Ports */
344 int config_frontside_crossbar_vsc3316(void)
346 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
347 u32 srds_prtcl_s1, srds_prtcl_s2;
350 ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS);
354 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
355 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
356 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
357 switch (srds_prtcl_s1) {
360 /* swap first lane and third lane on slot1 */
361 vsc3316_fsm1_tx[0][1] = 14;
362 vsc3316_fsm1_tx[6][1] = 0;
363 vsc3316_fsm1_rx[1][1] = 2;
364 vsc3316_fsm1_rx[6][1] = 13;
371 /* swap first lane and third lane on slot2 */
372 vsc3316_fsm1_tx[2][1] = 8;
373 vsc3316_fsm1_tx[4][1] = 6;
374 vsc3316_fsm1_rx[2][1] = 10;
375 vsc3316_fsm1_rx[5][1] = 5;
377 ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8);
380 ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8);
386 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
387 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
388 srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
389 switch (srds_prtcl_s2) {
392 /* swap first lane and third lane on slot3 */
393 vsc3316_fsm2_tx[2][1] = 11;
394 vsc3316_fsm2_tx[5][1] = 4;
395 vsc3316_fsm2_rx[2][1] = 9;
396 vsc3316_fsm2_rx[4][1] = 7;
409 /* swap first lane and third lane on slot4 */
410 vsc3316_fsm2_tx[6][1] = 3;
411 vsc3316_fsm2_tx[1][1] = 12;
412 vsc3316_fsm2_rx[0][1] = 1;
413 vsc3316_fsm2_rx[6][1] = 15;
415 ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8);
418 ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8);
427 int config_backside_crossbar_mux(void)
429 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
430 u32 srds_prtcl_s3, srds_prtcl_s4;
433 srds_prtcl_s3 = in_be32(&gur->rcwsr[4]) &
434 FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
435 srds_prtcl_s3 >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
436 switch (srds_prtcl_s3) {
438 /* SerDes3 is not enabled */
444 /* SD3(0:7) => SLOT5(0:7) */
445 brdcfg = QIXIS_READ(brdcfg[12]);
446 brdcfg &= ~BRDCFG12_SD3MX_MASK;
447 brdcfg |= BRDCFG12_SD3MX_SLOT5;
448 QIXIS_WRITE(brdcfg[12], brdcfg);
466 /* SD3(4:7) => SLOT6(0:3) */
467 brdcfg = QIXIS_READ(brdcfg[12]);
468 brdcfg &= ~BRDCFG12_SD3MX_MASK;
469 brdcfg |= BRDCFG12_SD3MX_SLOT6;
470 QIXIS_WRITE(brdcfg[12], brdcfg);
473 printf("WARNING: unsupported for SerDes3 Protocol %d\n",
478 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
479 FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
480 srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
481 switch (srds_prtcl_s4) {
483 /* SerDes4 is not enabled */
487 /* 10b, SD4(0:7) => SLOT7(0:7) */
488 brdcfg = QIXIS_READ(brdcfg[12]);
489 brdcfg &= ~BRDCFG12_SD4MX_MASK;
490 brdcfg |= BRDCFG12_SD4MX_SLOT7;
491 QIXIS_WRITE(brdcfg[12], brdcfg);
499 /* x1b, SD4(4:7) => SLOT8(0:3) */
500 brdcfg = QIXIS_READ(brdcfg[12]);
501 brdcfg &= ~BRDCFG12_SD4MX_MASK;
502 brdcfg |= BRDCFG12_SD4MX_SLOT8;
503 QIXIS_WRITE(brdcfg[12], brdcfg);
514 /* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */
515 brdcfg = QIXIS_READ(brdcfg[12]);
516 brdcfg &= ~BRDCFG12_SD4MX_MASK;
517 brdcfg |= BRDCFG12_SD4MX_AURO_SATA;
518 QIXIS_WRITE(brdcfg[12], brdcfg);
521 printf("WARNING: unsupported for SerDes4 Protocol %d\n",
529 int board_early_init_r(void)
531 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
532 int flash_esel = find_tlb_idx((void *)flashbase, 1);
535 * Remap Boot flash + PROMJET region to caching-inhibited
536 * so that flash can be erased properly.
539 /* Flush d-cache and invalidate i-cache of any FLASH data */
543 if (flash_esel == -1) {
544 /* very unlikely unless something is messed up */
545 puts("Error: Could not find TLB for FLASH BASE\n");
546 flash_esel = 2; /* give our best effort to continue */
548 /* invalidate existing TLB entry for flash + promjet */
549 disable_tlb(flash_esel);
552 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
553 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
554 0, flash_esel, BOOKE_PAGESZ_256M, 1);
556 /* Disable remote I2C connection to qixis fpga */
557 QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
560 * Adjust core voltage according to voltage ID
561 * This function changes I2C mux to channel 2.
564 printf("Warning: Adjusting core voltage failed.\n");
566 /* Configure board SERDES ports crossbar */
567 config_frontside_crossbar_vsc3316();
568 config_backside_crossbar_mux();
569 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
574 unsigned long get_board_sys_clk(void)
576 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
577 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
578 /* use accurate clock measurement */
579 int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
580 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
585 debug("SYS Clock measurement is: %d\n", val);
588 printf("Warning: SYS clock measurement is invalid, using value from brdcfg1.\n");
592 switch (sysclk_conf & 0x0F) {
593 case QIXIS_SYSCLK_83:
595 case QIXIS_SYSCLK_100:
597 case QIXIS_SYSCLK_125:
599 case QIXIS_SYSCLK_133:
601 case QIXIS_SYSCLK_150:
603 case QIXIS_SYSCLK_160:
605 case QIXIS_SYSCLK_166:
611 unsigned long get_board_ddr_clk(void)
613 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
614 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
615 /* use accurate clock measurement */
616 int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
617 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
622 debug("DDR Clock measurement is: %d\n", val);
625 printf("Warning: DDR clock measurement is invalid, using value from brdcfg1.\n");
629 switch ((ddrclk_conf & 0x30) >> 4) {
630 case QIXIS_DDRCLK_100:
632 case QIXIS_DDRCLK_125:
634 case QIXIS_DDRCLK_133:
640 int misc_init_r(void)
643 void *srds_base = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
644 serdes_corenet_t *srds_regs;
645 u32 actual[MAX_SERDES];
646 u32 pllcr0, expected;
649 sw = QIXIS_READ(brdcfg[2]);
650 for (i = 0; i < MAX_SERDES; i++) {
651 unsigned int clock = (sw >> (6 - 2 * i)) & 3;
654 actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
657 actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
660 actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
663 actual[i] = SRDS_PLLCR0_RFCK_SEL_161_13;
668 for (i = 0; i < MAX_SERDES; i++) {
669 srds_regs = srds_base + i * 0x1000;
670 pllcr0 = srds_regs->bank[0].pllcr0;
671 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
672 if (expected != actual[i]) {
673 printf("Warning: SERDES%u expects reference clock %sMHz, but actual is %sMHz\n",
674 i + 1, serdes_clock_to_string(expected),
675 serdes_clock_to_string(actual[i]));
682 int ft_board_setup(void *blob, bd_t *bd)
687 ft_cpu_setup(blob, bd);
689 base = env_get_bootm_low();
690 size = env_get_bootm_size();
692 fdt_fixup_memory(blob, (u64)base, (u64)size);
695 pci_of_setup(blob, bd);
698 fdt_fixup_liodn(blob);
699 fsl_fdt_fixup_dr_usb(blob, bd);
701 #ifdef CONFIG_SYS_DPAA_FMAN
702 fdt_fixup_fman_ethernet(blob);
703 fdt_fixup_board_enet(blob);
710 * This function is called by bdinfo to print detail board information.
711 * As an exmaple for future board, we organize the messages into
712 * several sections. If applicable, the message is in the format of
714 * It should aligned with normal output of bdinfo command.
716 * Voltage: Core, DDR and another configurable voltages
717 * Clock : Critical clocks which are not printed already
718 * RCW : RCW source if not printed already
719 * Misc : Other important information not in above catagories
721 void board_detail(void)
724 u8 brdcfg[16], dutcfg[16], rst_ctl;
726 static const char * const clk[] = {"66.67", "100", "125", "133.33"};
728 for (i = 0; i < 16; i++) {
729 brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
730 dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
734 if (!select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR)) {
735 vdd = read_voltage();
737 printf("Core voltage= %d mV\n", vdd);
738 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
741 printf("XVDD = 1.%d V\n", ((brdcfg[8] & 0xf) - 4) * 5 + 25);
744 printf("SYSCLK = %s MHz\nDDRCLK = %s MHz\n",
745 clk[(brdcfg[11] >> 2) & 0x3], clk[brdcfg[11] & 3]);
748 rcwsrc = (dutcfg[0] << 1) + (dutcfg[1] & 1);
749 puts("RCW source = ");
757 puts("16-bit NOR\n");
763 puts("SPI 16-bit addressing\n");
766 puts("SPI 24-bit addressing\n");
769 puts("I2C normal addressing\n");
772 puts("I2C extended addressing\n");
778 puts("8-bit NAND, 2KB\n");
781 if ((rcwsrc >= 0x080) && (rcwsrc <= 0x09f))
782 puts("Hard-coded RCW\n");
783 else if ((rcwsrc >= 0x110) && (rcwsrc <= 0x11f))
784 puts("8-bit NAND, 4KB\n");
791 rst_ctl = QIXIS_READ(rst_ctl);
792 puts("HRESET_REQ = ");
793 switch (rst_ctl & 0x30) {
798 puts("Assert HRESET\n");
801 puts("Reset system\n");
810 * Reverse engineering switch settings.
811 * Some bits cannot be figured out. They will be displayed as
812 * underscore in binary format. mask[] has those bits.
813 * Some bits are calculated differently than the actual switches
814 * if booting with overriding by FPGA.
816 void qixis_dump_switch(void)
822 * Any bit with 1 means that bit cannot be reverse engineered.
823 * It will be displayed as _ in binary format.
825 static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xcf, 0x3f, 0x1f};
827 u8 brdcfg[16], dutcfg[16];
829 for (i = 0; i < 16; i++) {
830 brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
831 dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
835 sw[1] = (dutcfg[1] << 0x07) |
836 ((dutcfg[12] & 0xC0) >> 1) |
837 ((dutcfg[11] & 0xE0) >> 3) |
838 ((dutcfg[6] & 0x80) >> 6) |
839 ((dutcfg[1] & 0x80) >> 7);
840 sw[2] = ((brdcfg[1] & 0x0f) << 4) |
841 ((brdcfg[1] & 0x30) >> 2) |
842 ((brdcfg[1] & 0x40) >> 5) |
843 ((brdcfg[1] & 0x80) >> 7);
845 sw[4] = ((dutcfg[2] & 0x01) << 7) |
846 ((dutcfg[2] & 0x06) << 4) |
847 ((~QIXIS_READ(present)) & 0x10) |
848 ((brdcfg[3] & 0x80) >> 4) |
849 ((brdcfg[3] & 0x01) << 2) |
850 ((brdcfg[6] == 0x62) ? 3 :
851 ((brdcfg[6] == 0x5a) ? 2 :
852 ((brdcfg[6] == 0x5e) ? 1 : 0)));
853 sw[5] = ((brdcfg[0] & 0x0f) << 4) |
854 ((QIXIS_READ(rst_ctl) & 0x30) >> 2) |
855 ((brdcfg[0] & 0x40) >> 5);
856 sw[6] = (brdcfg[11] & 0x20) |
857 ((brdcfg[5] & 0x02) << 3);
858 sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) |
859 ((brdcfg[5] & 0x10) << 2);
860 sw[8] = ((brdcfg[12] & 0x08) << 4) |
861 ((brdcfg[12] & 0x03) << 5);
863 puts("DIP switch (reverse-engineering)\n");
864 for (i = 0; i < 9; i++) {
865 printf("SW%d = 0b%s (0x%02x)\n",
866 i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
870 static int do_vdd_adjust(cmd_tbl_t *cmdtp,
877 return CMD_RET_USAGE;
878 if (!strict_strtoul(argv[1], 10, &override))
879 adjust_vdd(override); /* the value is checked by callee */
881 return CMD_RET_USAGE;
887 vdd_override, 2, 0, do_vdd_adjust,
889 "- override with the voltage specified in mV, eg. 1050"