1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2012 Freescale Semiconductor, Inc.
10 #include <fdt_support.h>
17 #include <linux/compiler.h>
19 #include <asm/processor.h>
20 #include <asm/cache.h>
21 #include <asm/immap_85xx.h>
22 #include <asm/fsl_law.h>
23 #include <asm/fsl_serdes.h>
24 #include <asm/fsl_liodn.h>
26 #include <linux/delay.h>
28 #include "../common/qixis.h"
29 #include "../common/vsc3316_3308.h"
31 #include "t4240qds_qixis.h"
33 DECLARE_GLOBAL_DATA_PTR;
35 static int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
36 {8, 8}, {9, 9}, {14, 14}, {15, 15} };
38 static int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
39 {10, 10}, {11, 11}, {12, 12}, {13, 13} };
41 static int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
42 {10, 11}, {11, 10}, {12, 2}, {13, 3} };
44 static int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
45 {8, 9}, {9, 8}, {14, 1}, {15, 0} };
51 struct cpu_type *cpu = gd->arch.cpu;
54 printf("Board: %sQDS, ", cpu->name);
55 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
56 QIXIS_READ(id), QIXIS_READ(arch));
58 sw = QIXIS_READ(brdcfg[0]);
59 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
62 printf("vBank: %d\n", sw);
68 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
70 printf("FPGA: v%d (%s), build %d",
71 (int)QIXIS_READ(scver), qixis_read_tag(buf),
72 (int)qixis_read_minor());
73 /* the timestamp string contains "\n" at the end */
74 printf(" on %s", qixis_read_time(buf));
77 * Display the actual SERDES reference clocks as configured by the
78 * dip switches on the board. Note that the SWx registers could
79 * technically be set to force the reference clocks to match the
80 * values that the SERDES expects (or vice versa). For now, however,
81 * we just display both values and hope the user notices when they
84 puts("SERDES Reference Clocks: ");
85 sw = QIXIS_READ(brdcfg[2]);
86 for (i = 0; i < MAX_SERDES; i++) {
87 static const char * const freq[] = {
88 "100", "125", "156.25", "161.1328125"};
89 unsigned int clock = (sw >> (6 - 2 * i)) & 3;
91 printf("SERDES%u=%sMHz ", i+1, freq[clock]);
98 int select_i2c_ch_pca9547(u8 ch, int bus_num)
105 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
108 printf("%s: Cannot find udev for a bus %d\n", __func__,
113 ret = dm_i2c_write(dev, 0, &ch, 1);
115 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
118 puts("PCA: failed to select proper channel\n");
126 * read_voltage from sensor on I2C bus
127 * We use average of 4 readings, waiting for 532us befor another reading
129 #define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */
130 #define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */
132 static inline int read_voltage(void)
134 int i, ret, voltage_read = 0;
141 for (i = 0; i < NUM_READINGS; i++) {
143 ret = i2c_get_chip_for_busnum(bus_num, I2C_VOL_MONITOR_ADDR,
146 printf("%s: Cannot find udev for a bus %d\n", __func__,
151 ret = dm_i2c_read(dev,
152 I2C_VOL_MONITOR_BUS_V_OFFSET,
153 (void *)&vol_mon, 2);
155 ret = i2c_read(I2C_VOL_MONITOR_ADDR,
156 I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
159 printf("VID: failed to read core voltage\n");
162 if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
163 printf("VID: Core voltage sensor error\n");
166 debug("VID: bus voltage reads 0x%04x\n", vol_mon);
168 voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
169 udelay(WAIT_FOR_ADC);
171 /* calculate the average */
172 voltage_read /= NUM_READINGS;
178 * We need to calculate how long before the voltage starts to drop or increase
179 * It returns with the loop count. Each loop takes several readings (532us)
181 static inline int wait_for_voltage_change(int vdd_last)
183 int timeout, vdd_current;
185 vdd_current = read_voltage();
186 /* wait until voltage starts to drop */
187 for (timeout = 0; abs(vdd_last - vdd_current) <= 4 &&
188 timeout < 100; timeout++) {
189 vdd_current = read_voltage();
191 if (timeout >= 100) {
192 printf("VID: Voltage adjustment timeout\n");
199 * argument 'wait' is the time we know the voltage difference can be measured
200 * this function keeps reading the voltage until it is stable
202 static inline int wait_for_voltage_stable(int wait)
204 int timeout, vdd_current, vdd_last;
206 vdd_last = read_voltage();
207 udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
208 /* wait until voltage is stable */
209 vdd_current = read_voltage();
210 for (timeout = 0; abs(vdd_last - vdd_current) >= 4 &&
211 timeout < 100; timeout++) {
212 vdd_last = vdd_current;
213 udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
214 vdd_current = read_voltage();
216 if (timeout >= 100) {
217 printf("VID: Voltage adjustment timeout\n");
224 static inline int set_voltage(u8 vid)
228 vdd_last = read_voltage();
229 QIXIS_WRITE(brdcfg[6], vid);
230 wait = wait_for_voltage_change(vdd_last);
233 debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC);
234 wait = wait ? wait : 1;
236 vdd_last = wait_for_voltage_stable(wait);
239 debug("VID: Current voltage is %d mV\n", vdd_last);
245 static int adjust_vdd(ulong vdd_override)
247 int re_enable = disable_interrupts();
248 ccsr_gur_t __iomem *gur =
249 (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
252 int vdd_target, vdd_current, vdd_last;
254 unsigned long vdd_string_override;
256 static const uint16_t vdd[32] = {
289 ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR, 0);
291 debug("VID: I2c failed to switch channel\n");
296 /* get the voltage ID from fuse status register */
297 fusesr = in_be32(&gur->dcfg_fusesr);
298 vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
299 FSL_CORENET_DCFG_FUSESR_VID_MASK;
300 if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) {
301 vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
302 FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
304 vdd_target = vdd[vid];
306 /* check override variable for overriding VDD */
307 vdd_string = env_get("t4240qds_vdd_mv");
308 if (vdd_override == 0 && vdd_string &&
309 !strict_strtoul(vdd_string, 10, &vdd_string_override))
310 vdd_override = vdd_string_override;
311 if (vdd_override >= 819 && vdd_override <= 1212) {
312 vdd_target = vdd_override * 10; /* convert to 1/10 mV */
313 debug("VDD override is %lu\n", vdd_override);
314 } else if (vdd_override != 0) {
315 printf("Invalid value.\n");
318 if (vdd_target == 0) {
319 debug("VID: VID not used\n");
323 /* round up and divice by 10 to get a value in mV */
324 vdd_target = DIV_ROUND_UP(vdd_target, 10);
325 debug("VID: vid = %d mV\n", vdd_target);
329 * Check current board VID setting
330 * Voltage regulator support output to 6.250mv step
331 * The highes voltage allowed for this board is (vid=0x40) 1.21250V
332 * the lowest is (vid=0x7f) 0.81875V
334 vid_current = QIXIS_READ(brdcfg[6]);
335 vdd_current = 121250 - (vid_current - 0x40) * 625;
336 debug("VID: Current vid setting is (0x%x) %d mV\n",
337 vid_current, vdd_current/100);
340 * Read voltage monitor to check real voltage.
341 * Voltage monitor LSB is 4mv.
343 vdd_last = read_voltage();
345 printf("VID: Could not read voltage sensor abort VID adjustment\n");
349 debug("VID: Core voltage is at %d mV\n", vdd_last);
351 * Adjust voltage to at or 8mV above target.
352 * Each step of adjustment is 6.25mV.
353 * Stepping down too fast may cause over current.
355 while (vdd_last > 0 && vid_current < 0x80 &&
356 vdd_last > (vdd_target + 8)) {
358 vdd_last = set_voltage(vid_current);
361 * Check if we need to step up
362 * This happens when board voltage switch was set too low
364 while (vdd_last > 0 && vid_current >= 0x40 &&
365 vdd_last < vdd_target + 2) {
367 vdd_last = set_voltage(vid_current);
370 printf("VID: Core voltage %d mV\n", vdd_last);
380 /* Configure Crossbar switches for Front-Side SerDes Ports */
381 int config_frontside_crossbar_vsc3316(void)
383 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
384 u32 srds_prtcl_s1, srds_prtcl_s2;
387 ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS, 0);
391 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
392 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
393 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
394 switch (srds_prtcl_s1) {
397 /* swap first lane and third lane on slot1 */
398 vsc3316_fsm1_tx[0][1] = 14;
399 vsc3316_fsm1_tx[6][1] = 0;
400 vsc3316_fsm1_rx[1][1] = 2;
401 vsc3316_fsm1_rx[6][1] = 13;
408 /* swap first lane and third lane on slot2 */
409 vsc3316_fsm1_tx[2][1] = 8;
410 vsc3316_fsm1_tx[4][1] = 6;
411 vsc3316_fsm1_rx[2][1] = 10;
412 vsc3316_fsm1_rx[5][1] = 5;
414 ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8);
417 ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8);
423 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
424 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
425 srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
426 switch (srds_prtcl_s2) {
429 /* swap first lane and third lane on slot3 */
430 vsc3316_fsm2_tx[2][1] = 11;
431 vsc3316_fsm2_tx[5][1] = 4;
432 vsc3316_fsm2_rx[2][1] = 9;
433 vsc3316_fsm2_rx[4][1] = 7;
446 /* swap first lane and third lane on slot4 */
447 vsc3316_fsm2_tx[6][1] = 3;
448 vsc3316_fsm2_tx[1][1] = 12;
449 vsc3316_fsm2_rx[0][1] = 1;
450 vsc3316_fsm2_rx[6][1] = 15;
452 ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8);
455 ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8);
464 int config_backside_crossbar_mux(void)
466 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
467 u32 srds_prtcl_s3, srds_prtcl_s4;
470 srds_prtcl_s3 = in_be32(&gur->rcwsr[4]) &
471 FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
472 srds_prtcl_s3 >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
473 switch (srds_prtcl_s3) {
475 /* SerDes3 is not enabled */
481 /* SD3(0:7) => SLOT5(0:7) */
482 brdcfg = QIXIS_READ(brdcfg[12]);
483 brdcfg &= ~BRDCFG12_SD3MX_MASK;
484 brdcfg |= BRDCFG12_SD3MX_SLOT5;
485 QIXIS_WRITE(brdcfg[12], brdcfg);
503 /* SD3(4:7) => SLOT6(0:3) */
504 brdcfg = QIXIS_READ(brdcfg[12]);
505 brdcfg &= ~BRDCFG12_SD3MX_MASK;
506 brdcfg |= BRDCFG12_SD3MX_SLOT6;
507 QIXIS_WRITE(brdcfg[12], brdcfg);
510 printf("WARNING: unsupported for SerDes3 Protocol %d\n",
515 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
516 FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
517 srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
518 switch (srds_prtcl_s4) {
520 /* SerDes4 is not enabled */
524 /* 10b, SD4(0:7) => SLOT7(0:7) */
525 brdcfg = QIXIS_READ(brdcfg[12]);
526 brdcfg &= ~BRDCFG12_SD4MX_MASK;
527 brdcfg |= BRDCFG12_SD4MX_SLOT7;
528 QIXIS_WRITE(brdcfg[12], brdcfg);
536 /* x1b, SD4(4:7) => SLOT8(0:3) */
537 brdcfg = QIXIS_READ(brdcfg[12]);
538 brdcfg &= ~BRDCFG12_SD4MX_MASK;
539 brdcfg |= BRDCFG12_SD4MX_SLOT8;
540 QIXIS_WRITE(brdcfg[12], brdcfg);
551 /* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */
552 brdcfg = QIXIS_READ(brdcfg[12]);
553 brdcfg &= ~BRDCFG12_SD4MX_MASK;
554 brdcfg |= BRDCFG12_SD4MX_AURO_SATA;
555 QIXIS_WRITE(brdcfg[12], brdcfg);
558 printf("WARNING: unsupported for SerDes4 Protocol %d\n",
566 int board_early_init_r(void)
568 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
569 int flash_esel = find_tlb_idx((void *)flashbase, 1);
572 * Remap Boot flash + PROMJET region to caching-inhibited
573 * so that flash can be erased properly.
576 /* Flush d-cache and invalidate i-cache of any FLASH data */
580 if (flash_esel == -1) {
581 /* very unlikely unless something is messed up */
582 puts("Error: Could not find TLB for FLASH BASE\n");
583 flash_esel = 2; /* give our best effort to continue */
585 /* invalidate existing TLB entry for flash + promjet */
586 disable_tlb(flash_esel);
589 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
590 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
591 0, flash_esel, BOOKE_PAGESZ_256M, 1);
593 /* Disable remote I2C connection to qixis fpga */
594 QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
597 * Adjust core voltage according to voltage ID
598 * This function changes I2C mux to channel 2.
601 printf("Warning: Adjusting core voltage failed.\n");
603 /* Configure board SERDES ports crossbar */
604 config_frontside_crossbar_vsc3316();
605 config_backside_crossbar_mux();
606 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
611 unsigned long get_board_sys_clk(void)
613 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
614 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
615 /* use accurate clock measurement */
616 int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
617 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
622 debug("SYS Clock measurement is: %d\n", val);
625 printf("Warning: SYS clock measurement is invalid, using value from brdcfg1.\n");
629 switch (sysclk_conf & 0x0F) {
630 case QIXIS_SYSCLK_83:
632 case QIXIS_SYSCLK_100:
634 case QIXIS_SYSCLK_125:
636 case QIXIS_SYSCLK_133:
638 case QIXIS_SYSCLK_150:
640 case QIXIS_SYSCLK_160:
642 case QIXIS_SYSCLK_166:
648 unsigned long get_board_ddr_clk(void)
650 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
651 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
652 /* use accurate clock measurement */
653 int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
654 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
659 debug("DDR Clock measurement is: %d\n", val);
662 printf("Warning: DDR clock measurement is invalid, using value from brdcfg1.\n");
666 switch ((ddrclk_conf & 0x30) >> 4) {
667 case QIXIS_DDRCLK_100:
669 case QIXIS_DDRCLK_125:
671 case QIXIS_DDRCLK_133:
677 int misc_init_r(void)
680 void *srds_base = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
681 serdes_corenet_t *srds_regs;
682 u32 actual[MAX_SERDES];
683 u32 pllcr0, expected;
686 sw = QIXIS_READ(brdcfg[2]);
687 for (i = 0; i < MAX_SERDES; i++) {
688 unsigned int clock = (sw >> (6 - 2 * i)) & 3;
691 actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
694 actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
697 actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
700 actual[i] = SRDS_PLLCR0_RFCK_SEL_161_13;
705 for (i = 0; i < MAX_SERDES; i++) {
706 srds_regs = srds_base + i * 0x1000;
707 pllcr0 = srds_regs->bank[0].pllcr0;
708 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
709 if (expected != actual[i]) {
710 printf("Warning: SERDES%u expects reference clock %sMHz, but actual is %sMHz\n",
711 i + 1, serdes_clock_to_string(expected),
712 serdes_clock_to_string(actual[i]));
719 int ft_board_setup(void *blob, bd_t *bd)
724 ft_cpu_setup(blob, bd);
726 base = env_get_bootm_low();
727 size = env_get_bootm_size();
729 fdt_fixup_memory(blob, (u64)base, (u64)size);
732 pci_of_setup(blob, bd);
735 fdt_fixup_liodn(blob);
736 fsl_fdt_fixup_dr_usb(blob, bd);
738 #ifdef CONFIG_SYS_DPAA_FMAN
739 fdt_fixup_fman_ethernet(blob);
740 fdt_fixup_board_enet(blob);
747 * This function is called by bdinfo to print detail board information.
748 * As an exmaple for future board, we organize the messages into
749 * several sections. If applicable, the message is in the format of
751 * It should aligned with normal output of bdinfo command.
753 * Voltage: Core, DDR and another configurable voltages
754 * Clock : Critical clocks which are not printed already
755 * RCW : RCW source if not printed already
756 * Misc : Other important information not in above catagories
758 void board_detail(void)
761 u8 brdcfg[16], dutcfg[16], rst_ctl;
763 static const char * const clk[] = {"66.67", "100", "125", "133.33"};
765 for (i = 0; i < 16; i++) {
766 brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
767 dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
771 if (!select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR, 0)) {
772 vdd = read_voltage();
774 printf("Core voltage= %d mV\n", vdd);
775 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
778 printf("XVDD = 1.%d V\n", ((brdcfg[8] & 0xf) - 4) * 5 + 25);
781 printf("SYSCLK = %s MHz\nDDRCLK = %s MHz\n",
782 clk[(brdcfg[11] >> 2) & 0x3], clk[brdcfg[11] & 3]);
785 rcwsrc = (dutcfg[0] << 1) + (dutcfg[1] & 1);
786 puts("RCW source = ");
794 puts("16-bit NOR\n");
800 puts("SPI 16-bit addressing\n");
803 puts("SPI 24-bit addressing\n");
806 puts("I2C normal addressing\n");
809 puts("I2C extended addressing\n");
815 puts("8-bit NAND, 2KB\n");
818 if ((rcwsrc >= 0x080) && (rcwsrc <= 0x09f))
819 puts("Hard-coded RCW\n");
820 else if ((rcwsrc >= 0x110) && (rcwsrc <= 0x11f))
821 puts("8-bit NAND, 4KB\n");
828 rst_ctl = QIXIS_READ(rst_ctl);
829 puts("HRESET_REQ = ");
830 switch (rst_ctl & 0x30) {
835 puts("Assert HRESET\n");
838 puts("Reset system\n");
847 * Reverse engineering switch settings.
848 * Some bits cannot be figured out. They will be displayed as
849 * underscore in binary format. mask[] has those bits.
850 * Some bits are calculated differently than the actual switches
851 * if booting with overriding by FPGA.
853 void qixis_dump_switch(void)
859 * Any bit with 1 means that bit cannot be reverse engineered.
860 * It will be displayed as _ in binary format.
862 static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xcf, 0x3f, 0x1f};
864 u8 brdcfg[16], dutcfg[16];
866 for (i = 0; i < 16; i++) {
867 brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
868 dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
872 sw[1] = (dutcfg[1] << 0x07) |
873 ((dutcfg[12] & 0xC0) >> 1) |
874 ((dutcfg[11] & 0xE0) >> 3) |
875 ((dutcfg[6] & 0x80) >> 6) |
876 ((dutcfg[1] & 0x80) >> 7);
877 sw[2] = ((brdcfg[1] & 0x0f) << 4) |
878 ((brdcfg[1] & 0x30) >> 2) |
879 ((brdcfg[1] & 0x40) >> 5) |
880 ((brdcfg[1] & 0x80) >> 7);
882 sw[4] = ((dutcfg[2] & 0x01) << 7) |
883 ((dutcfg[2] & 0x06) << 4) |
884 ((~QIXIS_READ(present)) & 0x10) |
885 ((brdcfg[3] & 0x80) >> 4) |
886 ((brdcfg[3] & 0x01) << 2) |
887 ((brdcfg[6] == 0x62) ? 3 :
888 ((brdcfg[6] == 0x5a) ? 2 :
889 ((brdcfg[6] == 0x5e) ? 1 : 0)));
890 sw[5] = ((brdcfg[0] & 0x0f) << 4) |
891 ((QIXIS_READ(rst_ctl) & 0x30) >> 2) |
892 ((brdcfg[0] & 0x40) >> 5);
893 sw[6] = (brdcfg[11] & 0x20) |
894 ((brdcfg[5] & 0x02) << 3);
895 sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) |
896 ((brdcfg[5] & 0x10) << 2);
897 sw[8] = ((brdcfg[12] & 0x08) << 4) |
898 ((brdcfg[12] & 0x03) << 5);
900 puts("DIP switch (reverse-engineering)\n");
901 for (i = 0; i < 9; i++) {
902 printf("SW%d = 0b%s (0x%02x)\n",
903 i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
907 static int do_vdd_adjust(struct cmd_tbl *cmdtp,
914 return CMD_RET_USAGE;
915 if (!strict_strtoul(argv[1], 10, &override))
916 adjust_vdd(override); /* the value is checked by callee */
918 return CMD_RET_USAGE;
924 vdd_override, 2, 0, do_vdd_adjust,
926 "- override with the voltage specified in mV, eg. 1050"