board/freescale/t4qds/eth.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2012 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <command.h>
   8 #include <fdt_support.h>
   9 #include <net.h>
  10 #include <netdev.h>
  11 #include <asm/mmu.h>
  12 #include <asm/processor.h>
  13 #include <asm/cache.h>
  14 #include <asm/immap_85xx.h>
  15 #include <asm/fsl_law.h>
  16 #include <fsl_ddr_sdram.h>
  17 #include <asm/fsl_serdes.h>
  18 #include <asm/fsl_portals.h>
  19 #include <asm/fsl_liodn.h>
  20 #include <malloc.h>
  21 #include <fm_eth.h>
  22 #include <fsl_mdio.h>
  23 #include <miiphy.h>
  24 #include <phy.h>
  25 #include <fsl_dtsec.h>
  26 #include <asm/fsl_serdes.h>
  27 #include <hwconfig.h>
  28 #include "../common/qixis.h"
  29 #include "../common/fman.h"
  30 #include <linux/libfdt.h>
  31
  32 #include "t4240qds_qixis.h"
  33
  34 #define EMI_NONE        0xFFFFFFFF
  35 #define EMI1_RGMII      0
  36 #define EMI1_SLOT1      1
  37 #define EMI1_SLOT2      2
  38 #define EMI1_SLOT3      3
  39 #define EMI1_SLOT4      4
  40 #define EMI1_SLOT5      5
  41 #define EMI1_SLOT7      7
  42 #define EMI2            8
  43 /* Slot6 and Slot8 do not have EMI connections */
  44
  45 static int mdio_mux[NUM_FM_PORTS];
  46
  47 static const char *mdio_names[] = {
  48         "T4240QDS_MDIO0",
  49         "T4240QDS_MDIO1",
  50         "T4240QDS_MDIO2",
  51         "T4240QDS_MDIO3",
  52         "T4240QDS_MDIO4",
  53         "T4240QDS_MDIO5",
  54         "NULL",
  55         "T4240QDS_MDIO7",
  56         "T4240QDS_10GC",
  57 };
  58
  59 static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2};
  60 static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4};
  61 static u8 slot_qsgmii_phyaddr[5][4] = {
  62         {0, 0, 0, 0},/* not used, to make index match slot No. */
  63         {0, 1, 2, 3},
  64         {4, 5, 6, 7},
  65         {8, 9, 0xa, 0xb},
  66         {0xc, 0xd, 0xe, 0xf},
  67 };
  68 static u8 qsgmiiphy_fix[NUM_FM_PORTS] = {0};
  69
  70 static const char *t4240qds_mdio_name_for_muxval(u8 muxval)
  71 {
  72         return mdio_names[muxval];
  73 }
  74
  75 struct mii_dev *mii_dev_for_muxval(u8 muxval)
  76 {
  77         struct mii_dev *bus;
  78         const char *name = t4240qds_mdio_name_for_muxval(muxval);
  79
  80         if (!name) {
  81                 printf("No bus for muxval %x\n", muxval);
  82                 return NULL;
  83         }
  84
  85         bus = miiphy_get_dev_by_name(name);
  86
  87         if (!bus) {
  88                 printf("No bus by name %s\n", name);
  89                 return NULL;
  90         }
  91
  92         return bus;
  93 }
  94
  95 struct t4240qds_mdio {
  96         u8 muxval;
  97         struct mii_dev *realbus;
  98 };
  99
 100 static void t4240qds_mux_mdio(u8 muxval)
 101 {
 102         u8 brdcfg4;
 103         if ((muxval < 6) || (muxval == 7)) {
 104                 brdcfg4 = QIXIS_READ(brdcfg[4]);
 105                 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
 106                 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
 107                 QIXIS_WRITE(brdcfg[4], brdcfg4);
 108         }
 109 }
 110
 111 static int t4240qds_mdio_read(struct mii_dev *bus, int addr, int devad,
 112                                 int regnum)
 113 {
 114         struct t4240qds_mdio *priv = bus->priv;
 115
 116         t4240qds_mux_mdio(priv->muxval);
 117
 118         return priv->realbus->read(priv->realbus, addr, devad, regnum);
 119 }
 120
 121 static int t4240qds_mdio_write(struct mii_dev *bus, int addr, int devad,
 122                                 int regnum, u16 value)
 123 {
 124         struct t4240qds_mdio *priv = bus->priv;
 125
 126         t4240qds_mux_mdio(priv->muxval);
 127
 128         return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
 129 }
 130
 131 static int t4240qds_mdio_reset(struct mii_dev *bus)
 132 {
 133         struct t4240qds_mdio *priv = bus->priv;
 134
 135         return priv->realbus->reset(priv->realbus);
 136 }
 137
 138 static int t4240qds_mdio_init(char *realbusname, u8 muxval)
 139 {
 140         struct t4240qds_mdio *pmdio;
 141         struct mii_dev *bus = mdio_alloc();
 142
 143         if (!bus) {
 144                 printf("Failed to allocate T4240QDS MDIO bus\n");
 145                 return -1;
 146         }
 147
 148         pmdio = malloc(sizeof(*pmdio));
 149         if (!pmdio) {
 150                 printf("Failed to allocate T4240QDS private data\n");
 151                 free(bus);
 152                 return -1;
 153         }
 154
 155         bus->read = t4240qds_mdio_read;
 156         bus->write = t4240qds_mdio_write;
 157         bus->reset = t4240qds_mdio_reset;
 158         strcpy(bus->name, t4240qds_mdio_name_for_muxval(muxval));
 159
 160         pmdio->realbus = miiphy_get_dev_by_name(realbusname);
 161
 162         if (!pmdio->realbus) {
 163                 printf("No bus with name %s\n", realbusname);
 164                 free(bus);
 165                 free(pmdio);
 166                 return -1;
 167         }
 168
 169         pmdio->muxval = muxval;
 170         bus->priv = pmdio;
 171
 172         return mdio_register(bus);
 173 }
 174
 175 void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
 176                                 enum fm_port port, int offset)
 177 {
 178         int interface = fm_info_get_enet_if(port);
 179         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 180         u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 181
 182         prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 183
 184         if (interface == PHY_INTERFACE_MODE_SGMII ||
 185             interface == PHY_INTERFACE_MODE_QSGMII) {
 186                 switch (port) {
 187                 case FM1_DTSEC1:
 188                         if (qsgmiiphy_fix[port])
 189                                 fdt_set_phy_handle(blob, prop, pa,
 190                                                    "sgmii_phy21");
 191                         break;
 192                 case FM1_DTSEC2:
 193                         if (qsgmiiphy_fix[port])
 194                                 fdt_set_phy_handle(blob, prop, pa,
 195                                                    "sgmii_phy22");
 196                         break;
 197                 case FM1_DTSEC3:
 198                         if (qsgmiiphy_fix[port])
 199                                 fdt_set_phy_handle(blob, prop, pa,
 200                                                    "sgmii_phy23");
 201                         break;
 202                 case FM1_DTSEC4:
 203                         if (qsgmiiphy_fix[port])
 204                                 fdt_set_phy_handle(blob, prop, pa,
 205                                                    "sgmii_phy24");
 206                         break;
 207                 case FM1_DTSEC6:
 208                         if (qsgmiiphy_fix[port])
 209                                 fdt_set_phy_handle(blob, prop, pa,
 210                                                    "sgmii_phy12");
 211                         break;
 212                 case FM1_DTSEC9:
 213                         if (qsgmiiphy_fix[port])
 214                                 fdt_set_phy_handle(blob, prop, pa,
 215                                                    "sgmii_phy14");
 216                         else
 217                                 fdt_set_phy_handle(blob, prop, pa,
 218                                                    "phy_sgmii4");
 219                         break;
 220                 case FM1_DTSEC10:
 221                         if (qsgmiiphy_fix[port])
 222                                 fdt_set_phy_handle(blob, prop, pa,
 223                                                    "sgmii_phy13");
 224                         else
 225                                 fdt_set_phy_handle(blob, prop, pa,
 226                                                    "phy_sgmii3");
 227                         break;
 228                 case FM2_DTSEC1:
 229                         if (qsgmiiphy_fix[port])
 230                                 fdt_set_phy_handle(blob, prop, pa,
 231                                                    "sgmii_phy41");
 232                         break;
 233                 case FM2_DTSEC2:
 234                         if (qsgmiiphy_fix[port])
 235                                 fdt_set_phy_handle(blob, prop, pa,
 236                                                    "sgmii_phy42");
 237                         break;
 238                 case FM2_DTSEC3:
 239                         if (qsgmiiphy_fix[port])
 240                                 fdt_set_phy_handle(blob, prop, pa,
 241                                                    "sgmii_phy43");
 242                         break;
 243                 case FM2_DTSEC4:
 244                         if (qsgmiiphy_fix[port])
 245                                 fdt_set_phy_handle(blob, prop, pa,
 246                                                    "sgmii_phy44");
 247                         break;
 248                 case FM2_DTSEC6:
 249                         if (qsgmiiphy_fix[port])
 250                                 fdt_set_phy_handle(blob, prop, pa,
 251                                                    "sgmii_phy32");
 252                         break;
 253                 case FM2_DTSEC9:
 254                         if (qsgmiiphy_fix[port])
 255                                 fdt_set_phy_handle(blob, prop, pa,
 256                                                    "sgmii_phy34");
 257                         else
 258                                 fdt_set_phy_handle(blob, prop, pa,
 259                                                    "phy_sgmii12");
 260                         break;
 261                 case FM2_DTSEC10:
 262                         if (qsgmiiphy_fix[port])
 263                                 fdt_set_phy_handle(blob, prop, pa,
 264                                                    "sgmii_phy33");
 265                         else
 266                                 fdt_set_phy_handle(blob, prop, pa,
 267                                                    "phy_sgmii11");
 268                         break;
 269                 default:
 270                         break;
 271                 }
 272         } else if (interface == PHY_INTERFACE_MODE_XGMII &&
 273                   ((prtcl2 == 55) || (prtcl2 == 57))) {
 274                 /*
 275                  * if the 10G is XFI, check hwconfig to see what is the
 276                  * media type, there are two types, fiber or copper,
 277                  * fix the dtb accordingly.
 278                  */
 279                 int media_type = 0;
 280                 struct fixed_link f_link;
 281                 char lane_mode[20] = {"10GBASE-KR"};
 282                 char buf[32] = "serdes-2,";
 283                 int off;
 284
 285                 switch (port) {
 286                 case FM1_10GEC1:
 287                         if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
 288                                 media_type = 1;
 289                                 fdt_set_phy_handle(blob, prop, pa,
 290                                                    "phy_xfi1");
 291                                 sprintf(buf, "%s%s%s", buf, "lane-a,",
 292                                         (char *)lane_mode);
 293                         }
 294                         break;
 295                 case FM1_10GEC2:
 296                         if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) {
 297                                 media_type = 1;
 298                                 fdt_set_phy_handle(blob, prop, pa,
 299                                                    "phy_xfi2");
 300                                 sprintf(buf, "%s%s%s", buf, "lane-b,",
 301                                         (char *)lane_mode);
 302                         }
 303                         break;
 304                 case FM2_10GEC1:
 305                         if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g1")) {
 306                                 media_type = 1;
 307                                 fdt_set_phy_handle(blob, prop, pa,
 308                                                    "phy_xfi3");
 309                                 sprintf(buf, "%s%s%s", buf, "lane-d,",
 310                                         (char *)lane_mode);
 311                         }
 312                         break;
 313                 case FM2_10GEC2:
 314                         if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g2")) {
 315                                 media_type = 1;
 316                                 fdt_set_phy_handle(blob, prop, pa,
 317                                                    "phy_xfi4");
 318                                 sprintf(buf, "%s%s%s", buf, "lane-c,",
 319                                         (char *)lane_mode);
 320                         }
 321                         break;
 322                 default:
 323                         return;
 324                 }
 325
 326                 if (!media_type) {
 327                         /* fixed-link is used for XFI fiber cable */
 328                         fdt_delprop(blob, offset, "phy-handle");
 329                         f_link.phy_id = port;
 330                         f_link.duplex = 1;
 331                         f_link.link_speed = 10000;
 332                         f_link.pause = 0;
 333                         f_link.asym_pause = 0;
 334                         fdt_setprop(blob, offset, "fixed-link", &f_link,
 335                                     sizeof(f_link));
 336                 } else {
 337                         /* set property for copper cable */
 338                         off = fdt_node_offset_by_compat_reg(blob,
 339                                         "fsl,fman-memac-mdio", pa + 0x1000);
 340                         fdt_setprop_string(blob, off, "lane-instance", buf);
 341                 }
 342         }
 343 }
 344
 345 void fdt_fixup_board_enet(void *fdt)
 346 {
 347         int i;
 348         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 349         u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 350
 351         prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 352         for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
 353                 switch (fm_info_get_enet_if(i)) {
 354                 case PHY_INTERFACE_MODE_SGMII:
 355                 case PHY_INTERFACE_MODE_QSGMII:
 356                         switch (mdio_mux[i]) {
 357                         case EMI1_SLOT1:
 358                                 fdt_status_okay_by_alias(fdt, "emi1_slot1");
 359                                 break;
 360                         case EMI1_SLOT2:
 361                                 fdt_status_okay_by_alias(fdt, "emi1_slot2");
 362                                 break;
 363                         case EMI1_SLOT3:
 364                                 fdt_status_okay_by_alias(fdt, "emi1_slot3");
 365                                 break;
 366                         case EMI1_SLOT4:
 367                                 fdt_status_okay_by_alias(fdt, "emi1_slot4");
 368                                 break;
 369                         default:
 370                                 break;
 371                         }
 372                         break;
 373                 case PHY_INTERFACE_MODE_XGMII:
 374                         /* check if it's XFI interface for 10g */
 375                         if ((prtcl2 == 55) || (prtcl2 == 57)) {
 376                                 if (i == FM1_10GEC1 && hwconfig_sub(
 377                                         "fsl_10gkr_copper", "fm1_10g1"))
 378                                         fdt_status_okay_by_alias(
 379                                         fdt, "xfi_pcs_mdio1");
 380                                 if (i == FM1_10GEC2 && hwconfig_sub(
 381                                         "fsl_10gkr_copper", "fm1_10g2"))
 382                                         fdt_status_okay_by_alias(
 383                                         fdt, "xfi_pcs_mdio2");
 384                                 if (i == FM2_10GEC1 && hwconfig_sub(
 385                                         "fsl_10gkr_copper", "fm2_10g1"))
 386                                         fdt_status_okay_by_alias(
 387                                         fdt, "xfi_pcs_mdio3");
 388                                 if (i == FM2_10GEC2 && hwconfig_sub(
 389                                         "fsl_10gkr_copper", "fm2_10g2"))
 390                                         fdt_status_okay_by_alias(
 391                                         fdt, "xfi_pcs_mdio4");
 392                                 break;
 393                         }
 394                         switch (i) {
 395                         case FM1_10GEC1:
 396                                 fdt_status_okay_by_alias(fdt, "emi2_xauislot1");
 397                                 break;
 398                         case FM1_10GEC2:
 399                                 fdt_status_okay_by_alias(fdt, "emi2_xauislot2");
 400                                 break;
 401                         case FM2_10GEC1:
 402                                 fdt_status_okay_by_alias(fdt, "emi2_xauislot3");
 403                                 break;
 404                         case FM2_10GEC2:
 405                                 fdt_status_okay_by_alias(fdt, "emi2_xauislot4");
 406                                 break;
 407                         default:
 408                                 break;
 409                         }
 410                         break;
 411                 default:
 412                         break;
 413                 }
 414         }
 415 }
 416
 417 static void initialize_qsgmiiphy_fix(void)
 418 {
 419         int i;
 420         unsigned short reg;
 421
 422         for (i = 1; i <= 4; i++) {
 423                 /*
 424                  * Try to read if a SGMII card is used, we do it slot by slot.
 425                  * if a SGMII PHY address is valid on a slot, then we mark
 426                  * all ports on the slot, then fix the PHY address for the
 427                  * marked port when doing dtb fixup.
 428                  */
 429                 if (miiphy_read(mdio_names[i],
 430                                 SGMII_CARD_PORT1_PHY_ADDR, MII_PHYSID2, &reg) != 0) {
 431                         debug("Slot%d PHY ID register 2 read failed\n", i);
 432                         continue;
 433                 }
 434
 435                 debug("Slot%d MII_PHYSID2 @ 0x1c= 0x%04x\n", i, reg);
 436
 437                 if (reg == 0xFFFF) {
 438                         /* No physical device present at this address */
 439                         continue;
 440                 }
 441
 442                 switch (i) {
 443                 case 1:
 444                         qsgmiiphy_fix[FM1_DTSEC5] = 1;
 445                         qsgmiiphy_fix[FM1_DTSEC6] = 1;
 446                         qsgmiiphy_fix[FM1_DTSEC9] = 1;
 447                         qsgmiiphy_fix[FM1_DTSEC10] = 1;
 448                         slot_qsgmii_phyaddr[1][0] =  SGMII_CARD_PORT1_PHY_ADDR;
 449                         slot_qsgmii_phyaddr[1][1] =  SGMII_CARD_PORT2_PHY_ADDR;
 450                         slot_qsgmii_phyaddr[1][2] =  SGMII_CARD_PORT3_PHY_ADDR;
 451                         slot_qsgmii_phyaddr[1][3] =  SGMII_CARD_PORT4_PHY_ADDR;
 452                         break;
 453                 case 2:
 454                         qsgmiiphy_fix[FM1_DTSEC1] = 1;
 455                         qsgmiiphy_fix[FM1_DTSEC2] = 1;
 456                         qsgmiiphy_fix[FM1_DTSEC3] = 1;
 457                         qsgmiiphy_fix[FM1_DTSEC4] = 1;
 458                         slot_qsgmii_phyaddr[2][0] =  SGMII_CARD_PORT1_PHY_ADDR;
 459                         slot_qsgmii_phyaddr[2][1] =  SGMII_CARD_PORT2_PHY_ADDR;
 460                         slot_qsgmii_phyaddr[2][2] =  SGMII_CARD_PORT3_PHY_ADDR;
 461                         slot_qsgmii_phyaddr[2][3] =  SGMII_CARD_PORT4_PHY_ADDR;
 462                         break;
 463                 case 3:
 464                         qsgmiiphy_fix[FM2_DTSEC5] = 1;
 465                         qsgmiiphy_fix[FM2_DTSEC6] = 1;
 466                         qsgmiiphy_fix[FM2_DTSEC9] = 1;
 467                         qsgmiiphy_fix[FM2_DTSEC10] = 1;
 468                         slot_qsgmii_phyaddr[3][0] =  SGMII_CARD_PORT1_PHY_ADDR;
 469                         slot_qsgmii_phyaddr[3][1] =  SGMII_CARD_PORT2_PHY_ADDR;
 470                         slot_qsgmii_phyaddr[3][2] =  SGMII_CARD_PORT3_PHY_ADDR;
 471                         slot_qsgmii_phyaddr[3][3] =  SGMII_CARD_PORT4_PHY_ADDR;
 472                         break;
 473                 case 4:
 474                         qsgmiiphy_fix[FM2_DTSEC1] = 1;
 475                         qsgmiiphy_fix[FM2_DTSEC2] = 1;
 476                         qsgmiiphy_fix[FM2_DTSEC3] = 1;
 477                         qsgmiiphy_fix[FM2_DTSEC4] = 1;
 478                         slot_qsgmii_phyaddr[4][0] =  SGMII_CARD_PORT1_PHY_ADDR;
 479                         slot_qsgmii_phyaddr[4][1] =  SGMII_CARD_PORT2_PHY_ADDR;
 480                         slot_qsgmii_phyaddr[4][2] =  SGMII_CARD_PORT3_PHY_ADDR;
 481                         slot_qsgmii_phyaddr[4][3] =  SGMII_CARD_PORT4_PHY_ADDR;
 482                         break;
 483                 default:
 484                         break;
 485                 }
 486         }
 487 }
 488
 489 int board_eth_init(bd_t *bis)
 490 {
 491 #if defined(CONFIG_FMAN_ENET)
 492         int i, idx, lane, slot, interface;
 493         struct memac_mdio_info dtsec_mdio_info;
 494         struct memac_mdio_info tgec_mdio_info;
 495         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 496         u32 srds_prtcl_s1, srds_prtcl_s2;
 497
 498         srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
 499                                         FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 500         srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 501         srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
 502                                         FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 503         srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 504
 505         /* Initialize the mdio_mux array so we can recognize empty elements */
 506         for (i = 0; i < NUM_FM_PORTS; i++)
 507                 mdio_mux[i] = EMI_NONE;
 508
 509         dtsec_mdio_info.regs =
 510                 (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
 511
 512         dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 513
 514         /* Register the 1G MDIO bus */
 515         fm_memac_mdio_init(bis, &dtsec_mdio_info);
 516
 517         tgec_mdio_info.regs =
 518                 (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
 519         tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
 520
 521         /* Register the 10G MDIO bus */
 522         fm_memac_mdio_init(bis, &tgec_mdio_info);
 523
 524         /* Register the muxing front-ends to the MDIO buses */
 525         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
 526         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
 527         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
 528         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
 529         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
 530         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
 531         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
 532         t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
 533
 534         initialize_qsgmiiphy_fix();
 535
 536         switch (srds_prtcl_s1) {
 537         case 1:
 538         case 2:
 539         case 4:
 540                 /* XAUI/HiGig in Slot1 and Slot2 */
 541                 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
 542                 fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
 543                 break;
 544         case 27:
 545         case 28:
 546         case 35:
 547         case 36:
 548                 /* SGMII in Slot1 and Slot2 */
 549                 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
 550                 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
 551                 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
 552                 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
 553                 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
 554                 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
 555                 if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
 556                         fm_info_set_phy_address(FM1_DTSEC9,
 557                                                 slot_qsgmii_phyaddr[1][3]);
 558                         fm_info_set_phy_address(FM1_DTSEC10,
 559                                                 slot_qsgmii_phyaddr[1][2]);
 560                 }
 561                 break;
 562         case 37:
 563         case 38:
 564                 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
 565                 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
 566                 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
 567                 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
 568                 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
 569                 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
 570                 if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
 571                         fm_info_set_phy_address(FM1_DTSEC9,
 572                                                 slot_qsgmii_phyaddr[1][2]);
 573                         fm_info_set_phy_address(FM1_DTSEC10,
 574                                                 slot_qsgmii_phyaddr[1][3]);
 575                 }
 576                 break;
 577         case 39:
 578         case 40:
 579         case 45:
 580         case 46:
 581         case 47:
 582         case 48:
 583                 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
 584                 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
 585                 if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
 586                         fm_info_set_phy_address(FM1_DTSEC10,
 587                                                 slot_qsgmii_phyaddr[1][2]);
 588                         fm_info_set_phy_address(FM1_DTSEC9,
 589                                                 slot_qsgmii_phyaddr[1][3]);
 590                 }
 591                 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
 592                 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
 593                 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
 594                 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
 595                 break;
 596         default:
 597                 puts("Invalid SerDes1 protocol for T4240QDS\n");
 598                 break;
 599         }
 600
 601         for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
 602                 idx = i - FM1_DTSEC1;
 603                 interface = fm_info_get_enet_if(i);
 604                 switch (interface) {
 605                 case PHY_INTERFACE_MODE_SGMII:
 606                 case PHY_INTERFACE_MODE_QSGMII:
 607                         if (interface == PHY_INTERFACE_MODE_QSGMII) {
 608                                 if (idx <= 3)
 609                                         lane = serdes_get_first_lane(FSL_SRDS_1,
 610                                                         QSGMII_FM1_A);
 611                                 else
 612                                         lane = serdes_get_first_lane(FSL_SRDS_1,
 613                                                         QSGMII_FM1_B);
 614                                 if (lane < 0)
 615                                         break;
 616                                 slot = lane_to_slot_fsm1[lane];
 617                                 debug("FM1@DTSEC%u expects QSGMII in slot %u\n",
 618                                       idx + 1, slot);
 619                         } else {
 620                                 lane = serdes_get_first_lane(FSL_SRDS_1,
 621                                                 SGMII_FM1_DTSEC1 + idx);
 622                                 if (lane < 0)
 623                                         break;
 624                                 slot = lane_to_slot_fsm1[lane];
 625                                 debug("FM1@DTSEC%u expects SGMII in slot %u\n",
 626                                       idx + 1, slot);
 627                         }
 628                         if (QIXIS_READ(present2) & (1 << (slot - 1)))
 629                                 fm_disable_port(i);
 630                         switch (slot) {
 631                         case 1:
 632                                 mdio_mux[i] = EMI1_SLOT1;
 633                                 fm_info_set_mdio(i,
 634                                         mii_dev_for_muxval(mdio_mux[i]));
 635                                 break;
 636                         case 2:
 637                                 mdio_mux[i] = EMI1_SLOT2;
 638                                 fm_info_set_mdio(i,
 639                                         mii_dev_for_muxval(mdio_mux[i]));
 640                                 break;
 641                         };
 642                         break;
 643                 case PHY_INTERFACE_MODE_RGMII:
 644                         /* FM1 DTSEC5 routes to RGMII with EC2 */
 645                         debug("FM1@DTSEC%u is RGMII at address %u\n",
 646                                 idx + 1, 2);
 647                         if (i == FM1_DTSEC5)
 648                                 fm_info_set_phy_address(i, 2);
 649                         mdio_mux[i] = EMI1_RGMII;
 650                         fm_info_set_mdio(i,
 651                                 mii_dev_for_muxval(mdio_mux[i]));
 652                         break;
 653                 default:
 654                         break;
 655                 }
 656         }
 657
 658         for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
 659                 idx = i - FM1_10GEC1;
 660                 switch (fm_info_get_enet_if(i)) {
 661                 case PHY_INTERFACE_MODE_XGMII:
 662                         if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) {
 663                                 /* A fake PHY address to make U-Boot happy */
 664                                 fm_info_set_phy_address(i, i);
 665                         } else {
 666                                 lane = serdes_get_first_lane(FSL_SRDS_1,
 667                                                 XAUI_FM1_MAC9 + idx);
 668                                 if (lane < 0)
 669                                         break;
 670                                 slot = lane_to_slot_fsm1[lane];
 671                                 if (QIXIS_READ(present2) & (1 << (slot - 1)))
 672                                         fm_disable_port(i);
 673                         }
 674                         mdio_mux[i] = EMI2;
 675                         fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 676                         break;
 677                 default:
 678                         break;
 679                 }
 680         }
 681
 682 #if (CONFIG_SYS_NUM_FMAN == 2)
 683         switch (srds_prtcl_s2) {
 684         case 1:
 685         case 2:
 686         case 4:
 687                 /* XAUI/HiGig in Slot3 and Slot4 */
 688                 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
 689                 fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR);
 690                 break;
 691         case 6:
 692         case 7:
 693         case 12:
 694         case 13:
 695         case 14:
 696         case 15:
 697         case 16:
 698         case 21:
 699         case 22:
 700         case 23:
 701         case 24:
 702         case 25:
 703         case 26:
 704                 /* XAUI/HiGig in Slot3, SGMII in Slot4 */
 705                 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
 706                 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
 707                 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
 708                 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 709                 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 710                 break;
 711         case 27:
 712         case 28:
 713         case 35:
 714         case 36:
 715                 /* SGMII in Slot3 and Slot4 */
 716                 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
 717                 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
 718                 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 719                 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 720                 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
 721                 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
 722                 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
 723                 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
 724                 break;
 725         case 37:
 726         case 38:
 727                 /* QSGMII in Slot3 and Slot4 */
 728                 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
 729                 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
 730                 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 731                 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 732                 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
 733                 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
 734                 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][2]);
 735                 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][3]);
 736                 break;
 737         case 39:
 738         case 40:
 739         case 45:
 740         case 46:
 741         case 47:
 742         case 48:
 743                 /* SGMII in Slot3 */
 744                 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
 745                 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
 746                 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
 747                 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
 748                 /* QSGMII in Slot4 */
 749                 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
 750                 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
 751                 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 752                 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 753                 break;
 754         case 49:
 755         case 50:
 756         case 51:
 757         case 52:
 758         case 53:
 759         case 54:
 760                 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
 761                 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
 762                 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
 763                 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 764                 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 765                 break;
 766         case 55:
 767         case 57:
 768                 /* XFI in Slot3, SGMII in Slot4 */
 769                 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
 770                 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
 771                 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 772                 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 773                 break;
 774         default:
 775                 puts("Invalid SerDes2 protocol for T4240QDS\n");
 776                 break;
 777         }
 778
 779         for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
 780                 idx = i - FM2_DTSEC1;
 781                 interface = fm_info_get_enet_if(i);
 782                 switch (interface) {
 783                 case PHY_INTERFACE_MODE_SGMII:
 784                 case PHY_INTERFACE_MODE_QSGMII:
 785                         if (interface == PHY_INTERFACE_MODE_QSGMII) {
 786                                 if (idx <= 3)
 787                                         lane = serdes_get_first_lane(FSL_SRDS_2,
 788                                                         QSGMII_FM2_A);
 789                                 else
 790                                         lane = serdes_get_first_lane(FSL_SRDS_2,
 791                                                         QSGMII_FM2_B);
 792                                 if (lane < 0)
 793                                         break;
 794                                 slot = lane_to_slot_fsm2[lane];
 795                                 debug("FM2@DTSEC%u expects QSGMII in slot %u\n",
 796                                       idx + 1, slot);
 797                         } else {
 798                                 lane = serdes_get_first_lane(FSL_SRDS_2,
 799                                                 SGMII_FM2_DTSEC1 + idx);
 800                                 if (lane < 0)
 801                                         break;
 802                                 slot = lane_to_slot_fsm2[lane];
 803                                 debug("FM2@DTSEC%u expects SGMII in slot %u\n",
 804                                       idx + 1, slot);
 805                         }
 806                         if (QIXIS_READ(present2) & (1 << (slot - 1)))
 807                                 fm_disable_port(i);
 808                         switch (slot) {
 809                         case 3:
 810                                 mdio_mux[i] = EMI1_SLOT3;
 811                                 fm_info_set_mdio(i,
 812                                         mii_dev_for_muxval(mdio_mux[i]));
 813                                 break;
 814                         case 4:
 815                                 mdio_mux[i] = EMI1_SLOT4;
 816                                 fm_info_set_mdio(i,
 817                                         mii_dev_for_muxval(mdio_mux[i]));
 818                                 break;
 819                         };
 820                         break;
 821                 case PHY_INTERFACE_MODE_RGMII:
 822                         /*
 823                          * If DTSEC5 is RGMII, then it's routed via via EC1 to
 824                          * the first on-board RGMII port.  If DTSEC6 is RGMII,
 825                          * then it's routed via via EC2 to the second on-board
 826                          * RGMII port.
 827                          */
 828                         debug("FM2@DTSEC%u is RGMII at address %u\n",
 829                                 idx + 1, i == FM2_DTSEC5 ? 1 : 2);
 830                         fm_info_set_phy_address(i, i == FM2_DTSEC5 ? 1 : 2);
 831                         mdio_mux[i] = EMI1_RGMII;
 832                         fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 833                         break;
 834                 default:
 835                         break;
 836                 }
 837         }
 838
 839         for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
 840                 idx = i - FM2_10GEC1;
 841                 switch (fm_info_get_enet_if(i)) {
 842                 case PHY_INTERFACE_MODE_XGMII:
 843                         if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) {
 844                                 /* A fake PHY address to make U-Boot happy */
 845                                 fm_info_set_phy_address(i, i);
 846                         } else {
 847                                 lane = serdes_get_first_lane(FSL_SRDS_2,
 848                                                 XAUI_FM2_MAC9 + idx);
 849                                 if (lane < 0)
 850                                         break;
 851                                 slot = lane_to_slot_fsm2[lane];
 852                                 if (QIXIS_READ(present2) & (1 << (slot - 1)))
 853                                         fm_disable_port(i);
 854                         }
 855                         mdio_mux[i] = EMI2;
 856                         fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 857                         break;
 858                 default:
 859                         break;
 860                 }
 861         }
 862 #endif /* CONFIG_SYS_NUM_FMAN */
 863
 864         cpu_eth_init(bis);
 865 #endif /* CONFIG_FMAN_ENET */
 866
 867         return pci_eth_init(bis);
 868 }