board/freescale/t4qds/eth.c

   1 /*
   2  * Copyright 2012 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <command.h>
  25 #include <netdev.h>
  26 #include <asm/mmu.h>
  27 #include <asm/processor.h>
  28 #include <asm/cache.h>
  29 #include <asm/immap_85xx.h>
  30 #include <asm/fsl_law.h>
  31 #include <asm/fsl_ddr_sdram.h>
  32 #include <asm/fsl_serdes.h>
  33 #include <asm/fsl_portals.h>
  34 #include <asm/fsl_liodn.h>
  35 #include <malloc.h>
  36 #include <fm_eth.h>
  37 #include <fsl_mdio.h>
  38 #include <miiphy.h>
  39 #include <phy.h>
  40 #include <asm/fsl_dtsec.h>
  41 #include <asm/fsl_serdes.h>
  42 #include "../common/qixis.h"
  43 #include "../common/fman.h"
  44
  45 #include "t4240qds_qixis.h"
  46
  47 #define EMI_NONE        0xFFFFFFFF
  48 #define EMI1_RGMII      0
  49 #define EMI1_SLOT1      1
  50 #define EMI1_SLOT2      2
  51 #define EMI1_SLOT3      3
  52 #define EMI1_SLOT4      4
  53 #define EMI1_SLOT5      5
  54 #define EMI1_SLOT7      7
  55 #define EMI2            8
  56 /* Slot6 and Slot8 do not have EMI connections */
  57
  58 static int mdio_mux[NUM_FM_PORTS];
  59
  60 static const char *mdio_names[] = {
  61         "T4240QDS_MDIO0",
  62         "T4240QDS_MDIO1",
  63         "T4240QDS_MDIO2",
  64         "T4240QDS_MDIO3",
  65         "T4240QDS_MDIO4",
  66         "T4240QDS_MDIO5",
  67         "NULL",
  68         "T4240QDS_MDIO7",
  69         "T4240QDS_10GC",
  70 };
  71
  72 static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2};
  73 static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4};
  74
  75 static const char *t4240qds_mdio_name_for_muxval(u8 muxval)
  76 {
  77         return mdio_names[muxval];
  78 }
  79
  80 struct mii_dev *mii_dev_for_muxval(u8 muxval)
  81 {
  82         struct mii_dev *bus;
  83         const char *name = t4240qds_mdio_name_for_muxval(muxval);
  84
  85         if (!name) {
  86                 printf("No bus for muxval %x\n", muxval);
  87                 return NULL;
  88         }
  89
  90         bus = miiphy_get_dev_by_name(name);
  91
  92         if (!bus) {
  93                 printf("No bus by name %s\n", name);
  94                 return NULL;
  95         }
  96
  97         return bus;
  98 }
  99
 100 struct t4240qds_mdio {
 101         u8 muxval;
 102         struct mii_dev *realbus;
 103 };
 104
 105 static void t4240qds_mux_mdio(u8 muxval)
 106 {
 107         u8 brdcfg4;
 108         if ((muxval < 6) || (muxval == 7)) {
 109                 brdcfg4 = QIXIS_READ(brdcfg[4]);
 110                 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
 111                 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
 112                 QIXIS_WRITE(brdcfg[4], brdcfg4);
 113         }
 114 }
 115
 116 static int t4240qds_mdio_read(struct mii_dev *bus, int addr, int devad,
 117                                 int regnum)
 118 {
 119         struct t4240qds_mdio *priv = bus->priv;
 120
 121         t4240qds_mux_mdio(priv->muxval);
 122
 123         return priv->realbus->read(priv->realbus, addr, devad, regnum);
 124 }
 125
 126 static int t4240qds_mdio_write(struct mii_dev *bus, int addr, int devad,
 127                                 int regnum, u16 value)
 128 {
 129         struct t4240qds_mdio *priv = bus->priv;
 130
 131         t4240qds_mux_mdio(priv->muxval);
 132
 133         return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
 134 }
 135
 136 static int t4240qds_mdio_reset(struct mii_dev *bus)
 137 {
 138         struct t4240qds_mdio *priv = bus->priv;
 139
 140         return priv->realbus->reset(priv->realbus);
 141 }
 142
 143 static int t4240qds_mdio_init(char *realbusname, u8 muxval)
 144 {
 145         struct t4240qds_mdio *pmdio;
 146         struct mii_dev *bus = mdio_alloc();
 147
 148         if (!bus) {
 149                 printf("Failed to allocate T4240QDS MDIO bus\n");
 150                 return -1;
 151         }
 152
 153         pmdio = malloc(sizeof(*pmdio));
 154         if (!pmdio) {
 155                 printf("Failed to allocate T4240QDS private data\n");
 156                 free(bus);
 157                 return -1;
 158         }
 159
 160         bus->read = t4240qds_mdio_read;
 161         bus->write = t4240qds_mdio_write;
 162         bus->reset = t4240qds_mdio_reset;
 163         sprintf(bus->name, t4240qds_mdio_name_for_muxval(muxval));
 164
 165         pmdio->realbus = miiphy_get_dev_by_name(realbusname);
 166
 167         if (!pmdio->realbus) {
 168                 printf("No bus with name %s\n", realbusname);
 169                 free(bus);
 170                 free(pmdio);
 171                 return -1;
 172         }
 173
 174         pmdio->muxval = muxval;
 175         bus->priv = pmdio;
 176
 177         return mdio_register(bus);
 178 }
 179
 180 void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
 181                                 enum fm_port port, int offset)
 182 {
 183         if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
 184                 switch (port) {
 185                 case FM1_DTSEC9:
 186                         fdt_set_phy_handle(blob, prop, pa, "phy_sgmii4");
 187                         break;
 188                 case FM1_DTSEC10:
 189                         fdt_set_phy_handle(blob, prop, pa, "phy_sgmii3");
 190                         break;
 191                 case FM2_DTSEC9:
 192                         fdt_set_phy_handle(blob, prop, pa, "phy_sgmii12");
 193                         break;
 194                 case FM2_DTSEC10:
 195                         fdt_set_phy_handle(blob, prop, pa, "phy_sgmii11");
 196                         break;
 197                 default:
 198                         break;
 199                 }
 200         }
 201 }
 202
 203 void fdt_fixup_board_enet(void *fdt)
 204 {
 205         int i;
 206         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 207         u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 208
 209         prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 210         for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
 211                 switch (fm_info_get_enet_if(i)) {
 212                 case PHY_INTERFACE_MODE_SGMII:
 213                         switch (mdio_mux[i]) {
 214                         case EMI1_SLOT1:
 215                                 fdt_status_okay_by_alias(fdt, "emi1_slot1");
 216                                 break;
 217                         case EMI1_SLOT2:
 218                                 fdt_status_okay_by_alias(fdt, "emi1_slot2");
 219                                 break;
 220                         case EMI1_SLOT3:
 221                                 fdt_status_okay_by_alias(fdt, "emi1_slot3");
 222                                 break;
 223                         case EMI1_SLOT4:
 224                                 fdt_status_okay_by_alias(fdt, "emi1_slot4");
 225                                 break;
 226                         default:
 227                                 break;
 228                         }
 229                         break;
 230                 case PHY_INTERFACE_MODE_XGMII:
 231                         /* check if it's XFI interface for 10g */
 232                         if ((prtcl2 == 56) || (prtcl2 == 57)) {
 233                                 fdt_status_okay_by_alias(fdt, "emi2_xfislot3");
 234                                 break;
 235                         }
 236                         switch (i) {
 237                         case FM1_10GEC1:
 238                                 fdt_status_okay_by_alias(fdt, "emi2_xauislot1");
 239                                 break;
 240                         case FM1_10GEC2:
 241                                 fdt_status_okay_by_alias(fdt, "emi2_xauislot2");
 242                                 break;
 243                         case FM2_10GEC1:
 244                                 fdt_status_okay_by_alias(fdt, "emi2_xauislot3");
 245                                 break;
 246                         case FM2_10GEC2:
 247                                 fdt_status_okay_by_alias(fdt, "emi2_xauislot4");
 248                                 break;
 249                         default:
 250                                 break;
 251                         }
 252                         break;
 253                 default:
 254                         break;
 255                 }
 256         }
 257 }
 258
 259 int board_eth_init(bd_t *bis)
 260 {
 261 #if defined(CONFIG_FMAN_ENET)
 262         int i, idx, lane, slot;
 263         struct memac_mdio_info dtsec_mdio_info;
 264         struct memac_mdio_info tgec_mdio_info;
 265         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 266         u32 srds_prtcl_s1, srds_prtcl_s2;
 267
 268         srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
 269                                         FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 270         srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 271         srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
 272                                         FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 273         srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 274
 275         /* Initialize the mdio_mux array so we can recognize empty elements */
 276         for (i = 0; i < NUM_FM_PORTS; i++)
 277                 mdio_mux[i] = EMI_NONE;
 278
 279         dtsec_mdio_info.regs =
 280                 (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
 281
 282         dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 283
 284         /* Register the 1G MDIO bus */
 285         fm_memac_mdio_init(bis, &dtsec_mdio_info);
 286
 287         tgec_mdio_info.regs =
 288                 (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
 289         tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
 290
 291         /* Register the 10G MDIO bus */
 292         fm_memac_mdio_init(bis, &tgec_mdio_info);
 293
 294         /* Register the muxing front-ends to the MDIO buses */
 295         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
 296         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
 297         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
 298         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
 299         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
 300         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
 301         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
 302         t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
 303
 304
 305         switch (srds_prtcl_s1) {
 306         case 1:
 307         case 2:
 308         case 4:
 309                 /* XAUI/HiGig in Slot1 and Slot2 */
 310                 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
 311                 fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
 312                 break;
 313         case 28:
 314         case 36:
 315                 /* SGMII in Slot1 and Slot2 */
 316                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
 317                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
 318                 fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
 319                 fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
 320                 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
 321                 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
 322                 if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
 323                         fm_info_set_phy_address(FM1_DTSEC9,
 324                                                 SGMII_CARD_PORT4_PHY_ADDR);
 325                         fm_info_set_phy_address(FM1_DTSEC10,
 326                                                 SGMII_CARD_PORT3_PHY_ADDR);
 327                 }
 328                 break;
 329         case 38:
 330                 fm_info_set_phy_address(FM1_DTSEC5, QSGMII_CARD_PHY_ADDR);
 331                 fm_info_set_phy_address(FM1_DTSEC6, QSGMII_CARD_PHY_ADDR);
 332                 if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
 333                         fm_info_set_phy_address(FM1_DTSEC9,
 334                                                 QSGMII_CARD_PHY_ADDR);
 335                         fm_info_set_phy_address(FM1_DTSEC10,
 336                                                 QSGMII_CARD_PHY_ADDR);
 337                 }
 338                 break;
 339         case 40:
 340         case 46:
 341         case 48:
 342                 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
 343                 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
 344                 if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
 345                         fm_info_set_phy_address(FM1_DTSEC10,
 346                                                 SGMII_CARD_PORT3_PHY_ADDR);
 347                         fm_info_set_phy_address(FM1_DTSEC9,
 348                                                 SGMII_CARD_PORT4_PHY_ADDR);
 349                 }
 350                 fm_info_set_phy_address(FM1_DTSEC1, QSGMII_CARD_PHY_ADDR);
 351                 fm_info_set_phy_address(FM1_DTSEC2, QSGMII_CARD_PHY_ADDR);
 352                 fm_info_set_phy_address(FM1_DTSEC3, QSGMII_CARD_PHY_ADDR);
 353                 fm_info_set_phy_address(FM1_DTSEC4, QSGMII_CARD_PHY_ADDR);
 354                 break;
 355         default:
 356                 puts("Invalid SerDes1 protocol for T4240QDS\n");
 357                 break;
 358         }
 359
 360         for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
 361                 idx = i - FM1_DTSEC1;
 362                 switch (fm_info_get_enet_if(i)) {
 363                 case PHY_INTERFACE_MODE_SGMII:
 364                         lane = serdes_get_first_lane(FSL_SRDS_1,
 365                                                 SGMII_FM1_DTSEC1 + idx);
 366                         if (lane < 0)
 367                                 break;
 368                         slot = lane_to_slot_fsm1[lane];
 369                         debug("FM1@DTSEC%u expects SGMII in slot %u\n",
 370                                 idx + 1, slot);
 371                         if (QIXIS_READ(present2) & (1 << (slot - 1)))
 372                                 fm_disable_port(i);
 373                         switch (slot) {
 374                         case 1:
 375                                 mdio_mux[i] = EMI1_SLOT1;
 376                                 fm_info_set_mdio(i,
 377                                         mii_dev_for_muxval(mdio_mux[i]));
 378                                 break;
 379                         case 2:
 380                                 mdio_mux[i] = EMI1_SLOT2;
 381                                 fm_info_set_mdio(i,
 382                                         mii_dev_for_muxval(mdio_mux[i]));
 383                                 break;
 384                         };
 385                         break;
 386                 case PHY_INTERFACE_MODE_RGMII:
 387                         /* FM1 DTSEC5 routes to RGMII with EC2 */
 388                         debug("FM1@DTSEC%u is RGMII at address %u\n",
 389                                 idx + 1, 2);
 390                         if (i == FM1_DTSEC5)
 391                                 fm_info_set_phy_address(i, 2);
 392                         mdio_mux[i] = EMI1_RGMII;
 393                         fm_info_set_mdio(i,
 394                                 mii_dev_for_muxval(mdio_mux[i]));
 395                         break;
 396                 default:
 397                         break;
 398                 }
 399         }
 400
 401         for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
 402                 idx = i - FM1_10GEC1;
 403                 switch (fm_info_get_enet_if(i)) {
 404                 case PHY_INTERFACE_MODE_XGMII:
 405                         lane = serdes_get_first_lane(FSL_SRDS_1,
 406                                                 XAUI_FM1_MAC9 + idx);
 407                         if (lane < 0)
 408                                 break;
 409                         slot = lane_to_slot_fsm1[lane];
 410                         if (QIXIS_READ(present2) & (1 << (slot - 1)))
 411                                 fm_disable_port(i);
 412                         mdio_mux[i] = EMI2;
 413                         fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 414                         break;
 415                 default:
 416                         break;
 417                 }
 418         }
 419
 420 #if (CONFIG_SYS_NUM_FMAN == 2)
 421         switch (srds_prtcl_s2) {
 422         case 1:
 423         case 2:
 424         case 4:
 425                 /* XAUI/HiGig in Slot3 and Slot4 */
 426                 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
 427                 fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR);
 428                 break;
 429         case 7:
 430         case 13:
 431         case 14:
 432         case 16:
 433         case 22:
 434         case 23:
 435         case 25:
 436         case 26:
 437                 /* XAUI/HiGig in Slot3, SGMII in Slot4 */
 438                 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
 439                 fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
 440                 fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
 441                 fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
 442                 fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
 443                 break;
 444         case 28:
 445         case 36:
 446                 /* SGMII in Slot3 and Slot4 */
 447                 fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
 448                 fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
 449                 fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
 450                 fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
 451                 fm_info_set_phy_address(FM2_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
 452                 fm_info_set_phy_address(FM2_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
 453                 fm_info_set_phy_address(FM2_DTSEC9, SGMII_CARD_PORT4_PHY_ADDR);
 454                 fm_info_set_phy_address(FM2_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
 455                 break;
 456         case 38:
 457                 /* QSGMII in Slot3 and Slot4 */
 458                 fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR);
 459                 fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR);
 460                 fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR);
 461                 fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR);
 462                 fm_info_set_phy_address(FM2_DTSEC5, QSGMII_CARD_PHY_ADDR);
 463                 fm_info_set_phy_address(FM2_DTSEC6, QSGMII_CARD_PHY_ADDR);
 464                 fm_info_set_phy_address(FM2_DTSEC9, QSGMII_CARD_PHY_ADDR);
 465                 fm_info_set_phy_address(FM2_DTSEC10, QSGMII_CARD_PHY_ADDR);
 466                 break;
 467         case 40:
 468         case 46:
 469         case 48:
 470                 /* SGMII in Slot3 */
 471                 fm_info_set_phy_address(FM2_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
 472                 fm_info_set_phy_address(FM2_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
 473                 fm_info_set_phy_address(FM2_DTSEC9, SGMII_CARD_PORT4_PHY_ADDR);
 474                 fm_info_set_phy_address(FM2_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
 475                 /* QSGMII in Slot4 */
 476                 fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR);
 477                 fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR);
 478                 fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR);
 479                 fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR);
 480                 break;
 481         case 50:
 482         case 52:
 483         case 54:
 484                 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
 485                 fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR);
 486                 fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR);
 487                 fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR);
 488                 fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR);
 489                 break;
 490         case 56:
 491         case 57:
 492                 /* XFI in Slot3, SGMII in Slot4 */
 493                 fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
 494                 fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
 495                 fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
 496                 fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
 497                 break;
 498         default:
 499                 puts("Invalid SerDes2 protocol for T4240QDS\n");
 500                 break;
 501         }
 502
 503         for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
 504                 idx = i - FM2_DTSEC1;
 505                 switch (fm_info_get_enet_if(i)) {
 506                 case PHY_INTERFACE_MODE_SGMII:
 507                         lane = serdes_get_first_lane(FSL_SRDS_2,
 508                                                 SGMII_FM2_DTSEC1 + idx);
 509                         if (lane < 0)
 510                                 break;
 511                         slot = lane_to_slot_fsm2[lane];
 512                         debug("FM2@DTSEC%u expects SGMII in slot %u\n",
 513                                 idx + 1, slot);
 514                         if (QIXIS_READ(present2) & (1 << (slot - 1)))
 515                                 fm_disable_port(i);
 516                         switch (slot) {
 517                         case 3:
 518                                 mdio_mux[i] = EMI1_SLOT3;
 519                                 fm_info_set_mdio(i,
 520                                         mii_dev_for_muxval(mdio_mux[i]));
 521                                 break;
 522                         case 4:
 523                                 mdio_mux[i] = EMI1_SLOT4;
 524                                 fm_info_set_mdio(i,
 525                                         mii_dev_for_muxval(mdio_mux[i]));
 526                                 break;
 527                         };
 528                         break;
 529                 case PHY_INTERFACE_MODE_RGMII:
 530                         /*
 531                          * If DTSEC5 is RGMII, then it's routed via via EC1 to
 532                          * the first on-board RGMII port.  If DTSEC6 is RGMII,
 533                          * then it's routed via via EC2 to the second on-board
 534                          * RGMII port.
 535                          */
 536                         debug("FM2@DTSEC%u is RGMII at address %u\n",
 537                                 idx + 1, i == FM2_DTSEC5 ? 1 : 2);
 538                         fm_info_set_phy_address(i, i == FM2_DTSEC5 ? 1 : 2);
 539                         mdio_mux[i] = EMI1_RGMII;
 540                         fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 541                         break;
 542                 default:
 543                         break;
 544                 }
 545         }
 546
 547         for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
 548                 idx = i - FM2_10GEC1;
 549                 switch (fm_info_get_enet_if(i)) {
 550                 case PHY_INTERFACE_MODE_XGMII:
 551                         lane = serdes_get_first_lane(FSL_SRDS_2,
 552                                                 XAUI_FM2_MAC9 + idx);
 553                         if (lane < 0)
 554                                 break;
 555                         slot = lane_to_slot_fsm2[lane];
 556                         if (QIXIS_READ(present2) & (1 << (slot - 1)))
 557                                 fm_disable_port(i);
 558                         mdio_mux[i] = EMI2;
 559                         fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 560                         break;
 561                 default:
 562                         break;
 563                 }
 564         }
 565 #endif /* CONFIG_SYS_NUM_FMAN */
 566
 567         cpu_eth_init(bis);
 568 #endif /* CONFIG_FMAN_ENET */
 569
 570         return pci_eth_init(bis);
 571 }