board/freescale/t4qds/eth.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2012 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <command.h>
   8 #include <fdt_support.h>
   9 #include <log.h>
  10 #include <net.h>
  11 #include <netdev.h>
  12 #include <asm/mmu.h>
  13 #include <asm/processor.h>
  14 #include <asm/cache.h>
  15 #include <asm/immap_85xx.h>
  16 #include <asm/fsl_law.h>
  17 #include <fsl_ddr_sdram.h>
  18 #include <asm/fsl_serdes.h>
  19 #include <asm/fsl_portals.h>
  20 #include <asm/fsl_liodn.h>
  21 #include <malloc.h>
  22 #include <fm_eth.h>
  23 #include <fsl_mdio.h>
  24 #include <miiphy.h>
  25 #include <phy.h>
  26 #include <fsl_dtsec.h>
  27 #include <asm/fsl_serdes.h>
  28 #include <hwconfig.h>
  29 #include "../common/qixis.h"
  30 #include "../common/fman.h"
  31 #include <linux/libfdt.h>
  32
  33 #include "t4240qds_qixis.h"
  34
  35 #define EMI_NONE        0xFFFFFFFF
  36 #define EMI1_RGMII      0
  37 #define EMI1_SLOT1      1
  38 #define EMI1_SLOT2      2
  39 #define EMI1_SLOT3      3
  40 #define EMI1_SLOT4      4
  41 #define EMI1_SLOT5      5
  42 #define EMI1_SLOT7      7
  43 #define EMI2            8
  44 /* Slot6 and Slot8 do not have EMI connections */
  45
  46 static int mdio_mux[NUM_FM_PORTS];
  47
  48 static const char *mdio_names[] = {
  49         "T4240QDS_MDIO0",
  50         "T4240QDS_MDIO1",
  51         "T4240QDS_MDIO2",
  52         "T4240QDS_MDIO3",
  53         "T4240QDS_MDIO4",
  54         "T4240QDS_MDIO5",
  55         "NULL",
  56         "T4240QDS_MDIO7",
  57         "T4240QDS_10GC",
  58 };
  59
  60 static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2};
  61 static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4};
  62 static u8 slot_qsgmii_phyaddr[5][4] = {
  63         {0, 0, 0, 0},/* not used, to make index match slot No. */
  64         {0, 1, 2, 3},
  65         {4, 5, 6, 7},
  66         {8, 9, 0xa, 0xb},
  67         {0xc, 0xd, 0xe, 0xf},
  68 };
  69 static u8 qsgmiiphy_fix[NUM_FM_PORTS] = {0};
  70
  71 static const char *t4240qds_mdio_name_for_muxval(u8 muxval)
  72 {
  73         return mdio_names[muxval];
  74 }
  75
  76 struct mii_dev *mii_dev_for_muxval(u8 muxval)
  77 {
  78         struct mii_dev *bus;
  79         const char *name = t4240qds_mdio_name_for_muxval(muxval);
  80
  81         if (!name) {
  82                 printf("No bus for muxval %x\n", muxval);
  83                 return NULL;
  84         }
  85
  86         bus = miiphy_get_dev_by_name(name);
  87
  88         if (!bus) {
  89                 printf("No bus by name %s\n", name);
  90                 return NULL;
  91         }
  92
  93         return bus;
  94 }
  95
  96 struct t4240qds_mdio {
  97         u8 muxval;
  98         struct mii_dev *realbus;
  99 };
 100
 101 static void t4240qds_mux_mdio(u8 muxval)
 102 {
 103         u8 brdcfg4;
 104         if ((muxval < 6) || (muxval == 7)) {
 105                 brdcfg4 = QIXIS_READ(brdcfg[4]);
 106                 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
 107                 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
 108                 QIXIS_WRITE(brdcfg[4], brdcfg4);
 109         }
 110 }
 111
 112 static int t4240qds_mdio_read(struct mii_dev *bus, int addr, int devad,
 113                                 int regnum)
 114 {
 115         struct t4240qds_mdio *priv = bus->priv;
 116
 117         t4240qds_mux_mdio(priv->muxval);
 118
 119         return priv->realbus->read(priv->realbus, addr, devad, regnum);
 120 }
 121
 122 static int t4240qds_mdio_write(struct mii_dev *bus, int addr, int devad,
 123                                 int regnum, u16 value)
 124 {
 125         struct t4240qds_mdio *priv = bus->priv;
 126
 127         t4240qds_mux_mdio(priv->muxval);
 128
 129         return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
 130 }
 131
 132 static int t4240qds_mdio_reset(struct mii_dev *bus)
 133 {
 134         struct t4240qds_mdio *priv = bus->priv;
 135
 136         return priv->realbus->reset(priv->realbus);
 137 }
 138
 139 static int t4240qds_mdio_init(char *realbusname, u8 muxval)
 140 {
 141         struct t4240qds_mdio *pmdio;
 142         struct mii_dev *bus = mdio_alloc();
 143
 144         if (!bus) {
 145                 printf("Failed to allocate T4240QDS MDIO bus\n");
 146                 return -1;
 147         }
 148
 149         pmdio = malloc(sizeof(*pmdio));
 150         if (!pmdio) {
 151                 printf("Failed to allocate T4240QDS private data\n");
 152                 free(bus);
 153                 return -1;
 154         }
 155
 156         bus->read = t4240qds_mdio_read;
 157         bus->write = t4240qds_mdio_write;
 158         bus->reset = t4240qds_mdio_reset;
 159         strcpy(bus->name, t4240qds_mdio_name_for_muxval(muxval));
 160
 161         pmdio->realbus = miiphy_get_dev_by_name(realbusname);
 162
 163         if (!pmdio->realbus) {
 164                 printf("No bus with name %s\n", realbusname);
 165                 free(bus);
 166                 free(pmdio);
 167                 return -1;
 168         }
 169
 170         pmdio->muxval = muxval;
 171         bus->priv = pmdio;
 172
 173         return mdio_register(bus);
 174 }
 175
 176 void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
 177                                 enum fm_port port, int offset)
 178 {
 179         int interface = fm_info_get_enet_if(port);
 180         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 181         u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 182
 183         prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 184
 185         if (interface == PHY_INTERFACE_MODE_SGMII ||
 186             interface == PHY_INTERFACE_MODE_QSGMII) {
 187                 switch (port) {
 188                 case FM1_DTSEC1:
 189                         if (qsgmiiphy_fix[port])
 190                                 fdt_set_phy_handle(blob, prop, pa,
 191                                                    "sgmii_phy21");
 192                         break;
 193                 case FM1_DTSEC2:
 194                         if (qsgmiiphy_fix[port])
 195                                 fdt_set_phy_handle(blob, prop, pa,
 196                                                    "sgmii_phy22");
 197                         break;
 198                 case FM1_DTSEC3:
 199                         if (qsgmiiphy_fix[port])
 200                                 fdt_set_phy_handle(blob, prop, pa,
 201                                                    "sgmii_phy23");
 202                         break;
 203                 case FM1_DTSEC4:
 204                         if (qsgmiiphy_fix[port])
 205                                 fdt_set_phy_handle(blob, prop, pa,
 206                                                    "sgmii_phy24");
 207                         break;
 208                 case FM1_DTSEC6:
 209                         if (qsgmiiphy_fix[port])
 210                                 fdt_set_phy_handle(blob, prop, pa,
 211                                                    "sgmii_phy12");
 212                         break;
 213                 case FM1_DTSEC9:
 214                         if (qsgmiiphy_fix[port])
 215                                 fdt_set_phy_handle(blob, prop, pa,
 216                                                    "sgmii_phy14");
 217                         else
 218                                 fdt_set_phy_handle(blob, prop, pa,
 219                                                    "phy_sgmii4");
 220                         break;
 221                 case FM1_DTSEC10:
 222                         if (qsgmiiphy_fix[port])
 223                                 fdt_set_phy_handle(blob, prop, pa,
 224                                                    "sgmii_phy13");
 225                         else
 226                                 fdt_set_phy_handle(blob, prop, pa,
 227                                                    "phy_sgmii3");
 228                         break;
 229                 case FM2_DTSEC1:
 230                         if (qsgmiiphy_fix[port])
 231                                 fdt_set_phy_handle(blob, prop, pa,
 232                                                    "sgmii_phy41");
 233                         break;
 234                 case FM2_DTSEC2:
 235                         if (qsgmiiphy_fix[port])
 236                                 fdt_set_phy_handle(blob, prop, pa,
 237                                                    "sgmii_phy42");
 238                         break;
 239                 case FM2_DTSEC3:
 240                         if (qsgmiiphy_fix[port])
 241                                 fdt_set_phy_handle(blob, prop, pa,
 242                                                    "sgmii_phy43");
 243                         break;
 244                 case FM2_DTSEC4:
 245                         if (qsgmiiphy_fix[port])
 246                                 fdt_set_phy_handle(blob, prop, pa,
 247                                                    "sgmii_phy44");
 248                         break;
 249                 case FM2_DTSEC6:
 250                         if (qsgmiiphy_fix[port])
 251                                 fdt_set_phy_handle(blob, prop, pa,
 252                                                    "sgmii_phy32");
 253                         break;
 254                 case FM2_DTSEC9:
 255                         if (qsgmiiphy_fix[port])
 256                                 fdt_set_phy_handle(blob, prop, pa,
 257                                                    "sgmii_phy34");
 258                         else
 259                                 fdt_set_phy_handle(blob, prop, pa,
 260                                                    "phy_sgmii12");
 261                         break;
 262                 case FM2_DTSEC10:
 263                         if (qsgmiiphy_fix[port])
 264                                 fdt_set_phy_handle(blob, prop, pa,
 265                                                    "sgmii_phy33");
 266                         else
 267                                 fdt_set_phy_handle(blob, prop, pa,
 268                                                    "phy_sgmii11");
 269                         break;
 270                 default:
 271                         break;
 272                 }
 273         } else if (interface == PHY_INTERFACE_MODE_XGMII &&
 274                   ((prtcl2 == 55) || (prtcl2 == 57))) {
 275                 /*
 276                  * if the 10G is XFI, check hwconfig to see what is the
 277                  * media type, there are two types, fiber or copper,
 278                  * fix the dtb accordingly.
 279                  */
 280                 int media_type = 0;
 281                 struct fixed_link f_link;
 282                 char lane_mode[20] = {"10GBASE-KR"};
 283                 char buf[32] = "serdes-2,";
 284                 int off;
 285
 286                 switch (port) {
 287                 case FM1_10GEC1:
 288                         if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
 289                                 media_type = 1;
 290                                 fdt_set_phy_handle(blob, prop, pa,
 291                                                    "phy_xfi1");
 292                                 sprintf(buf, "%s%s%s", buf, "lane-a,",
 293                                         (char *)lane_mode);
 294                         }
 295                         break;
 296                 case FM1_10GEC2:
 297                         if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) {
 298                                 media_type = 1;
 299                                 fdt_set_phy_handle(blob, prop, pa,
 300                                                    "phy_xfi2");
 301                                 sprintf(buf, "%s%s%s", buf, "lane-b,",
 302                                         (char *)lane_mode);
 303                         }
 304                         break;
 305                 case FM2_10GEC1:
 306                         if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g1")) {
 307                                 media_type = 1;
 308                                 fdt_set_phy_handle(blob, prop, pa,
 309                                                    "phy_xfi3");
 310                                 sprintf(buf, "%s%s%s", buf, "lane-d,",
 311                                         (char *)lane_mode);
 312                         }
 313                         break;
 314                 case FM2_10GEC2:
 315                         if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g2")) {
 316                                 media_type = 1;
 317                                 fdt_set_phy_handle(blob, prop, pa,
 318                                                    "phy_xfi4");
 319                                 sprintf(buf, "%s%s%s", buf, "lane-c,",
 320                                         (char *)lane_mode);
 321                         }
 322                         break;
 323                 default:
 324                         return;
 325                 }
 326
 327                 if (!media_type) {
 328                         /* fixed-link is used for XFI fiber cable */
 329                         fdt_delprop(blob, offset, "phy-handle");
 330                         f_link.phy_id = port;
 331                         f_link.duplex = 1;
 332                         f_link.link_speed = 10000;
 333                         f_link.pause = 0;
 334                         f_link.asym_pause = 0;
 335                         fdt_setprop(blob, offset, "fixed-link", &f_link,
 336                                     sizeof(f_link));
 337                 } else {
 338                         /* set property for copper cable */
 339                         off = fdt_node_offset_by_compat_reg(blob,
 340                                         "fsl,fman-memac-mdio", pa + 0x1000);
 341                         fdt_setprop_string(blob, off, "lane-instance", buf);
 342                 }
 343         }
 344 }
 345
 346 void fdt_fixup_board_enet(void *fdt)
 347 {
 348         int i;
 349         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 350         u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 351
 352         prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 353         for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
 354                 switch (fm_info_get_enet_if(i)) {
 355                 case PHY_INTERFACE_MODE_SGMII:
 356                 case PHY_INTERFACE_MODE_QSGMII:
 357                         switch (mdio_mux[i]) {
 358                         case EMI1_SLOT1:
 359                                 fdt_status_okay_by_alias(fdt, "emi1_slot1");
 360                                 break;
 361                         case EMI1_SLOT2:
 362                                 fdt_status_okay_by_alias(fdt, "emi1_slot2");
 363                                 break;
 364                         case EMI1_SLOT3:
 365                                 fdt_status_okay_by_alias(fdt, "emi1_slot3");
 366                                 break;
 367                         case EMI1_SLOT4:
 368                                 fdt_status_okay_by_alias(fdt, "emi1_slot4");
 369                                 break;
 370                         default:
 371                                 break;
 372                         }
 373                         break;
 374                 case PHY_INTERFACE_MODE_XGMII:
 375                         /* check if it's XFI interface for 10g */
 376                         if ((prtcl2 == 55) || (prtcl2 == 57)) {
 377                                 if (i == FM1_10GEC1 && hwconfig_sub(
 378                                         "fsl_10gkr_copper", "fm1_10g1"))
 379                                         fdt_status_okay_by_alias(
 380                                         fdt, "xfi_pcs_mdio1");
 381                                 if (i == FM1_10GEC2 && hwconfig_sub(
 382                                         "fsl_10gkr_copper", "fm1_10g2"))
 383                                         fdt_status_okay_by_alias(
 384                                         fdt, "xfi_pcs_mdio2");
 385                                 if (i == FM2_10GEC1 && hwconfig_sub(
 386                                         "fsl_10gkr_copper", "fm2_10g1"))
 387                                         fdt_status_okay_by_alias(
 388                                         fdt, "xfi_pcs_mdio3");
 389                                 if (i == FM2_10GEC2 && hwconfig_sub(
 390                                         "fsl_10gkr_copper", "fm2_10g2"))
 391                                         fdt_status_okay_by_alias(
 392                                         fdt, "xfi_pcs_mdio4");
 393                                 break;
 394                         }
 395                         switch (i) {
 396                         case FM1_10GEC1:
 397                                 fdt_status_okay_by_alias(fdt, "emi2_xauislot1");
 398                                 break;
 399                         case FM1_10GEC2:
 400                                 fdt_status_okay_by_alias(fdt, "emi2_xauislot2");
 401                                 break;
 402                         case FM2_10GEC1:
 403                                 fdt_status_okay_by_alias(fdt, "emi2_xauislot3");
 404                                 break;
 405                         case FM2_10GEC2:
 406                                 fdt_status_okay_by_alias(fdt, "emi2_xauislot4");
 407                                 break;
 408                         default:
 409                                 break;
 410                         }
 411                         break;
 412                 default:
 413                         break;
 414                 }
 415         }
 416 }
 417
 418 static void initialize_qsgmiiphy_fix(void)
 419 {
 420         int i;
 421         unsigned short reg;
 422
 423         for (i = 1; i <= 4; i++) {
 424                 /*
 425                  * Try to read if a SGMII card is used, we do it slot by slot.
 426                  * if a SGMII PHY address is valid on a slot, then we mark
 427                  * all ports on the slot, then fix the PHY address for the
 428                  * marked port when doing dtb fixup.
 429                  */
 430                 if (miiphy_read(mdio_names[i],
 431                                 SGMII_CARD_PORT1_PHY_ADDR, MII_PHYSID2, &reg) != 0) {
 432                         debug("Slot%d PHY ID register 2 read failed\n", i);
 433                         continue;
 434                 }
 435
 436                 debug("Slot%d MII_PHYSID2 @ 0x1c= 0x%04x\n", i, reg);
 437
 438                 if (reg == 0xFFFF) {
 439                         /* No physical device present at this address */
 440                         continue;
 441                 }
 442
 443                 switch (i) {
 444                 case 1:
 445                         qsgmiiphy_fix[FM1_DTSEC5] = 1;
 446                         qsgmiiphy_fix[FM1_DTSEC6] = 1;
 447                         qsgmiiphy_fix[FM1_DTSEC9] = 1;
 448                         qsgmiiphy_fix[FM1_DTSEC10] = 1;
 449                         slot_qsgmii_phyaddr[1][0] =  SGMII_CARD_PORT1_PHY_ADDR;
 450                         slot_qsgmii_phyaddr[1][1] =  SGMII_CARD_PORT2_PHY_ADDR;
 451                         slot_qsgmii_phyaddr[1][2] =  SGMII_CARD_PORT3_PHY_ADDR;
 452                         slot_qsgmii_phyaddr[1][3] =  SGMII_CARD_PORT4_PHY_ADDR;
 453                         break;
 454                 case 2:
 455                         qsgmiiphy_fix[FM1_DTSEC1] = 1;
 456                         qsgmiiphy_fix[FM1_DTSEC2] = 1;
 457                         qsgmiiphy_fix[FM1_DTSEC3] = 1;
 458                         qsgmiiphy_fix[FM1_DTSEC4] = 1;
 459                         slot_qsgmii_phyaddr[2][0] =  SGMII_CARD_PORT1_PHY_ADDR;
 460                         slot_qsgmii_phyaddr[2][1] =  SGMII_CARD_PORT2_PHY_ADDR;
 461                         slot_qsgmii_phyaddr[2][2] =  SGMII_CARD_PORT3_PHY_ADDR;
 462                         slot_qsgmii_phyaddr[2][3] =  SGMII_CARD_PORT4_PHY_ADDR;
 463                         break;
 464                 case 3:
 465                         qsgmiiphy_fix[FM2_DTSEC5] = 1;
 466                         qsgmiiphy_fix[FM2_DTSEC6] = 1;
 467                         qsgmiiphy_fix[FM2_DTSEC9] = 1;
 468                         qsgmiiphy_fix[FM2_DTSEC10] = 1;
 469                         slot_qsgmii_phyaddr[3][0] =  SGMII_CARD_PORT1_PHY_ADDR;
 470                         slot_qsgmii_phyaddr[3][1] =  SGMII_CARD_PORT2_PHY_ADDR;
 471                         slot_qsgmii_phyaddr[3][2] =  SGMII_CARD_PORT3_PHY_ADDR;
 472                         slot_qsgmii_phyaddr[3][3] =  SGMII_CARD_PORT4_PHY_ADDR;
 473                         break;
 474                 case 4:
 475                         qsgmiiphy_fix[FM2_DTSEC1] = 1;
 476                         qsgmiiphy_fix[FM2_DTSEC2] = 1;
 477                         qsgmiiphy_fix[FM2_DTSEC3] = 1;
 478                         qsgmiiphy_fix[FM2_DTSEC4] = 1;
 479                         slot_qsgmii_phyaddr[4][0] =  SGMII_CARD_PORT1_PHY_ADDR;
 480                         slot_qsgmii_phyaddr[4][1] =  SGMII_CARD_PORT2_PHY_ADDR;
 481                         slot_qsgmii_phyaddr[4][2] =  SGMII_CARD_PORT3_PHY_ADDR;
 482                         slot_qsgmii_phyaddr[4][3] =  SGMII_CARD_PORT4_PHY_ADDR;
 483                         break;
 484                 default:
 485                         break;
 486                 }
 487         }
 488 }
 489
 490 int board_eth_init(bd_t *bis)
 491 {
 492 #if defined(CONFIG_FMAN_ENET)
 493         int i, idx, lane, slot, interface;
 494         struct memac_mdio_info dtsec_mdio_info;
 495         struct memac_mdio_info tgec_mdio_info;
 496         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 497         u32 srds_prtcl_s1, srds_prtcl_s2;
 498
 499         srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
 500                                         FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 501         srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 502         srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
 503                                         FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 504         srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 505
 506         /* Initialize the mdio_mux array so we can recognize empty elements */
 507         for (i = 0; i < NUM_FM_PORTS; i++)
 508                 mdio_mux[i] = EMI_NONE;
 509
 510         dtsec_mdio_info.regs =
 511                 (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
 512
 513         dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 514
 515         /* Register the 1G MDIO bus */
 516         fm_memac_mdio_init(bis, &dtsec_mdio_info);
 517
 518         tgec_mdio_info.regs =
 519                 (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
 520         tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
 521
 522         /* Register the 10G MDIO bus */
 523         fm_memac_mdio_init(bis, &tgec_mdio_info);
 524
 525         /* Register the muxing front-ends to the MDIO buses */
 526         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
 527         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
 528         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
 529         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
 530         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
 531         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
 532         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
 533         t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
 534
 535         initialize_qsgmiiphy_fix();
 536
 537         switch (srds_prtcl_s1) {
 538         case 1:
 539         case 2:
 540         case 4:
 541                 /* XAUI/HiGig in Slot1 and Slot2 */
 542                 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
 543                 fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
 544                 break;
 545         case 27:
 546         case 28:
 547         case 35:
 548         case 36:
 549                 /* SGMII in Slot1 and Slot2 */
 550                 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
 551                 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
 552                 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
 553                 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
 554                 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
 555                 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
 556                 if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
 557                         fm_info_set_phy_address(FM1_DTSEC9,
 558                                                 slot_qsgmii_phyaddr[1][3]);
 559                         fm_info_set_phy_address(FM1_DTSEC10,
 560                                                 slot_qsgmii_phyaddr[1][2]);
 561                 }
 562                 break;
 563         case 37:
 564         case 38:
 565                 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
 566                 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
 567                 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
 568                 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
 569                 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
 570                 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
 571                 if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
 572                         fm_info_set_phy_address(FM1_DTSEC9,
 573                                                 slot_qsgmii_phyaddr[1][2]);
 574                         fm_info_set_phy_address(FM1_DTSEC10,
 575                                                 slot_qsgmii_phyaddr[1][3]);
 576                 }
 577                 break;
 578         case 39:
 579         case 40:
 580         case 45:
 581         case 46:
 582         case 47:
 583         case 48:
 584                 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
 585                 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
 586                 if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
 587                         fm_info_set_phy_address(FM1_DTSEC10,
 588                                                 slot_qsgmii_phyaddr[1][2]);
 589                         fm_info_set_phy_address(FM1_DTSEC9,
 590                                                 slot_qsgmii_phyaddr[1][3]);
 591                 }
 592                 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
 593                 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
 594                 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
 595                 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
 596                 break;
 597         default:
 598                 puts("Invalid SerDes1 protocol for T4240QDS\n");
 599                 break;
 600         }
 601
 602         for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
 603                 idx = i - FM1_DTSEC1;
 604                 interface = fm_info_get_enet_if(i);
 605                 switch (interface) {
 606                 case PHY_INTERFACE_MODE_SGMII:
 607                 case PHY_INTERFACE_MODE_QSGMII:
 608                         if (interface == PHY_INTERFACE_MODE_QSGMII) {
 609                                 if (idx <= 3)
 610                                         lane = serdes_get_first_lane(FSL_SRDS_1,
 611                                                         QSGMII_FM1_A);
 612                                 else
 613                                         lane = serdes_get_first_lane(FSL_SRDS_1,
 614                                                         QSGMII_FM1_B);
 615                                 if (lane < 0)
 616                                         break;
 617                                 slot = lane_to_slot_fsm1[lane];
 618                                 debug("FM1@DTSEC%u expects QSGMII in slot %u\n",
 619                                       idx + 1, slot);
 620                         } else {
 621                                 lane = serdes_get_first_lane(FSL_SRDS_1,
 622                                                 SGMII_FM1_DTSEC1 + idx);
 623                                 if (lane < 0)
 624                                         break;
 625                                 slot = lane_to_slot_fsm1[lane];
 626                                 debug("FM1@DTSEC%u expects SGMII in slot %u\n",
 627                                       idx + 1, slot);
 628                         }
 629                         if (QIXIS_READ(present2) & (1 << (slot - 1)))
 630                                 fm_disable_port(i);
 631                         switch (slot) {
 632                         case 1:
 633                                 mdio_mux[i] = EMI1_SLOT1;
 634                                 fm_info_set_mdio(i,
 635                                         mii_dev_for_muxval(mdio_mux[i]));
 636                                 break;
 637                         case 2:
 638                                 mdio_mux[i] = EMI1_SLOT2;
 639                                 fm_info_set_mdio(i,
 640                                         mii_dev_for_muxval(mdio_mux[i]));
 641                                 break;
 642                         };
 643                         break;
 644                 case PHY_INTERFACE_MODE_RGMII:
 645                         /* FM1 DTSEC5 routes to RGMII with EC2 */
 646                         debug("FM1@DTSEC%u is RGMII at address %u\n",
 647                                 idx + 1, 2);
 648                         if (i == FM1_DTSEC5)
 649                                 fm_info_set_phy_address(i, 2);
 650                         mdio_mux[i] = EMI1_RGMII;
 651                         fm_info_set_mdio(i,
 652                                 mii_dev_for_muxval(mdio_mux[i]));
 653                         break;
 654                 default:
 655                         break;
 656                 }
 657         }
 658
 659         for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
 660                 idx = i - FM1_10GEC1;
 661                 switch (fm_info_get_enet_if(i)) {
 662                 case PHY_INTERFACE_MODE_XGMII:
 663                         if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) {
 664                                 /* A fake PHY address to make U-Boot happy */
 665                                 fm_info_set_phy_address(i, i);
 666                         } else {
 667                                 lane = serdes_get_first_lane(FSL_SRDS_1,
 668                                                 XAUI_FM1_MAC9 + idx);
 669                                 if (lane < 0)
 670                                         break;
 671                                 slot = lane_to_slot_fsm1[lane];
 672                                 if (QIXIS_READ(present2) & (1 << (slot - 1)))
 673                                         fm_disable_port(i);
 674                         }
 675                         mdio_mux[i] = EMI2;
 676                         fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 677                         break;
 678                 default:
 679                         break;
 680                 }
 681         }
 682
 683 #if (CONFIG_SYS_NUM_FMAN == 2)
 684         switch (srds_prtcl_s2) {
 685         case 1:
 686         case 2:
 687         case 4:
 688                 /* XAUI/HiGig in Slot3 and Slot4 */
 689                 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
 690                 fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR);
 691                 break;
 692         case 6:
 693         case 7:
 694         case 12:
 695         case 13:
 696         case 14:
 697         case 15:
 698         case 16:
 699         case 21:
 700         case 22:
 701         case 23:
 702         case 24:
 703         case 25:
 704         case 26:
 705                 /* XAUI/HiGig in Slot3, SGMII in Slot4 */
 706                 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
 707                 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
 708                 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
 709                 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 710                 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 711                 break;
 712         case 27:
 713         case 28:
 714         case 35:
 715         case 36:
 716                 /* SGMII in Slot3 and Slot4 */
 717                 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
 718                 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
 719                 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 720                 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 721                 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
 722                 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
 723                 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
 724                 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
 725                 break;
 726         case 37:
 727         case 38:
 728                 /* QSGMII in Slot3 and Slot4 */
 729                 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
 730                 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
 731                 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 732                 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 733                 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
 734                 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
 735                 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][2]);
 736                 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][3]);
 737                 break;
 738         case 39:
 739         case 40:
 740         case 45:
 741         case 46:
 742         case 47:
 743         case 48:
 744                 /* SGMII in Slot3 */
 745                 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
 746                 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
 747                 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
 748                 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
 749                 /* QSGMII in Slot4 */
 750                 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
 751                 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
 752                 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 753                 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 754                 break;
 755         case 49:
 756         case 50:
 757         case 51:
 758         case 52:
 759         case 53:
 760         case 54:
 761                 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
 762                 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
 763                 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
 764                 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 765                 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 766                 break;
 767         case 55:
 768         case 57:
 769                 /* XFI in Slot3, SGMII in Slot4 */
 770                 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
 771                 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
 772                 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 773                 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 774                 break;
 775         default:
 776                 puts("Invalid SerDes2 protocol for T4240QDS\n");
 777                 break;
 778         }
 779
 780         for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
 781                 idx = i - FM2_DTSEC1;
 782                 interface = fm_info_get_enet_if(i);
 783                 switch (interface) {
 784                 case PHY_INTERFACE_MODE_SGMII:
 785                 case PHY_INTERFACE_MODE_QSGMII:
 786                         if (interface == PHY_INTERFACE_MODE_QSGMII) {
 787                                 if (idx <= 3)
 788                                         lane = serdes_get_first_lane(FSL_SRDS_2,
 789                                                         QSGMII_FM2_A);
 790                                 else
 791                                         lane = serdes_get_first_lane(FSL_SRDS_2,
 792                                                         QSGMII_FM2_B);
 793                                 if (lane < 0)
 794                                         break;
 795                                 slot = lane_to_slot_fsm2[lane];
 796                                 debug("FM2@DTSEC%u expects QSGMII in slot %u\n",
 797                                       idx + 1, slot);
 798                         } else {
 799                                 lane = serdes_get_first_lane(FSL_SRDS_2,
 800                                                 SGMII_FM2_DTSEC1 + idx);
 801                                 if (lane < 0)
 802                                         break;
 803                                 slot = lane_to_slot_fsm2[lane];
 804                                 debug("FM2@DTSEC%u expects SGMII in slot %u\n",
 805                                       idx + 1, slot);
 806                         }
 807                         if (QIXIS_READ(present2) & (1 << (slot - 1)))
 808                                 fm_disable_port(i);
 809                         switch (slot) {
 810                         case 3:
 811                                 mdio_mux[i] = EMI1_SLOT3;
 812                                 fm_info_set_mdio(i,
 813                                         mii_dev_for_muxval(mdio_mux[i]));
 814                                 break;
 815                         case 4:
 816                                 mdio_mux[i] = EMI1_SLOT4;
 817                                 fm_info_set_mdio(i,
 818                                         mii_dev_for_muxval(mdio_mux[i]));
 819                                 break;
 820                         };
 821                         break;
 822                 case PHY_INTERFACE_MODE_RGMII:
 823                         /*
 824                          * If DTSEC5 is RGMII, then it's routed via via EC1 to
 825                          * the first on-board RGMII port.  If DTSEC6 is RGMII,
 826                          * then it's routed via via EC2 to the second on-board
 827                          * RGMII port.
 828                          */
 829                         debug("FM2@DTSEC%u is RGMII at address %u\n",
 830                                 idx + 1, i == FM2_DTSEC5 ? 1 : 2);
 831                         fm_info_set_phy_address(i, i == FM2_DTSEC5 ? 1 : 2);
 832                         mdio_mux[i] = EMI1_RGMII;
 833                         fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 834                         break;
 835                 default:
 836                         break;
 837                 }
 838         }
 839
 840         for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
 841                 idx = i - FM2_10GEC1;
 842                 switch (fm_info_get_enet_if(i)) {
 843                 case PHY_INTERFACE_MODE_XGMII:
 844                         if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) {
 845                                 /* A fake PHY address to make U-Boot happy */
 846                                 fm_info_set_phy_address(i, i);
 847                         } else {
 848                                 lane = serdes_get_first_lane(FSL_SRDS_2,
 849                                                 XAUI_FM2_MAC9 + idx);
 850                                 if (lane < 0)
 851                                         break;
 852                                 slot = lane_to_slot_fsm2[lane];
 853                                 if (QIXIS_READ(present2) & (1 << (slot - 1)))
 854                                         fm_disable_port(i);
 855                         }
 856                         mdio_mux[i] = EMI2;
 857                         fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 858                         break;
 859                 default:
 860                         break;
 861                 }
 862         }
 863 #endif /* CONFIG_SYS_NUM_FMAN */
 864
 865         cpu_eth_init(bis);
 866 #endif /* CONFIG_FMAN_ENET */
 867
 868         return pci_eth_init(bis);
 869 }