board/freescale/t4qds/ddr.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2012 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <i2c.h>
   8 #include <hwconfig.h>
   9 #include <init.h>
  10 #include <log.h>
  11 #include <asm/mmu.h>
  12 #include <fsl_ddr_sdram.h>
  13 #include <fsl_ddr_dimm_params.h>
  14 #include <asm/fsl_law.h>
  15 #include "ddr.h"
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 void fsl_ddr_board_options(memctl_options_t *popts,
  20                                 dimm_params_t *pdimm,
  21                                 unsigned int ctrl_num)
  22 {
  23         const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  24         ulong ddr_freq;
  25
  26         if (ctrl_num > 2) {
  27                 printf("Not supported controller number %d\n", ctrl_num);
  28                 return;
  29         }
  30         if (!pdimm->n_ranks)
  31                 return;
  32
  33         /*
  34          * we use identical timing for all slots. If needed, change the code
  35          * to  pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
  36          */
  37         if (popts->registered_dimm_en)
  38                 pbsp = rdimms[0];
  39         else
  40                 pbsp = udimms[0];
  41
  42
  43         /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
  44          * freqency and n_banks specified in board_specific_parameters table.
  45          */
  46         ddr_freq = get_ddr_freq(0) / 1000000;
  47         while (pbsp->datarate_mhz_high) {
  48                 if (pbsp->n_ranks == pdimm->n_ranks &&
  49                     (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
  50                         if (ddr_freq <= pbsp->datarate_mhz_high) {
  51                                 popts->cpo_override = pbsp->cpo;
  52                                 popts->write_data_delay =
  53                                         pbsp->write_data_delay;
  54                                 popts->clk_adjust = pbsp->clk_adjust;
  55                                 popts->wrlvl_start = pbsp->wrlvl_start;
  56                                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  57                                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  58                                 popts->twot_en = pbsp->force_2t;
  59                                 goto found;
  60                         }
  61                         pbsp_highest = pbsp;
  62                 }
  63                 pbsp++;
  64         }
  65
  66         if (pbsp_highest) {
  67                 printf("Error: board specific timing not found "
  68                         "for data rate %lu MT/s\n"
  69                         "Trying to use the highest speed (%u) parameters\n",
  70                         ddr_freq, pbsp_highest->datarate_mhz_high);
  71                 popts->cpo_override = pbsp_highest->cpo;
  72                 popts->write_data_delay = pbsp_highest->write_data_delay;
  73                 popts->clk_adjust = pbsp_highest->clk_adjust;
  74                 popts->wrlvl_start = pbsp_highest->wrlvl_start;
  75                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  76                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  77                 popts->twot_en = pbsp_highest->force_2t;
  78         } else {
  79                 panic("DIMM is not supported by this board");
  80         }
  81 found:
  82         debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
  83                 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
  84                 "wrlvl_ctrl_3 0x%x\n",
  85                 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
  86                 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
  87                 pbsp->wrlvl_ctl_3);
  88
  89         /*
  90          * Factors to consider for half-strength driver enable:
  91          *      - number of DIMMs installed
  92          */
  93         popts->half_strength_driver_enable = 0;
  94         /*
  95          * Write leveling override
  96          */
  97         popts->wrlvl_override = 1;
  98         popts->wrlvl_sample = 0xf;
  99
 100         /*
 101          * Rtt and Rtt_WR override
 102          */
 103         popts->rtt_override = 0;
 104
 105         /* Enable ZQ calibration */
 106         popts->zq_en = 1;
 107
 108         /* DHC_EN =1, ODT = 75 Ohm */
 109         popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
 110         popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
 111
 112         /* optimize cpo for erratum A-009942 */
 113         popts->cpo_sample = 0x63;
 114 }
 115
 116 int dram_init(void)
 117 {
 118         phys_size_t dram_size;
 119
 120         puts("Initializing....using SPD\n");
 121
 122 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 123         dram_size = fsl_ddr_sdram();
 124 #else
 125         /* DDR has been initialised by first stage boot loader */
 126         dram_size = fsl_ddr_sdram_size();
 127 #endif
 128         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 129         dram_size *= 0x100000;
 130
 131         gd->ram_size = dram_size;
 132
 133         return 0;
 134 }