3ac61f009c90acf01333173d77cc5bf7433dcb0f
[platform/kernel/u-boot.git] / board / freescale / t208xrdb / t208xrdb.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2009-2013 Freescale Semiconductor, Inc.
4  */
5
6 #include <common.h>
7 #include <command.h>
8 #include <env.h>
9 #include <i2c.h>
10 #include <init.h>
11 #include <netdev.h>
12 #include <linux/compiler.h>
13 #include <asm/mmu.h>
14 #include <asm/processor.h>
15 #include <asm/immap_85xx.h>
16 #include <asm/fsl_law.h>
17 #include <asm/fsl_serdes.h>
18 #include <asm/fsl_liodn.h>
19 #include <fm_eth.h>
20 #include "t208xrdb.h"
21 #include "cpld.h"
22 #include "../common/vid.h"
23
24 DECLARE_GLOBAL_DATA_PTR;
25
26 int checkboard(void)
27 {
28         struct cpu_type *cpu = gd->arch.cpu;
29         static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
30
31         printf("Board: %sRDB, ", cpu->name);
32         printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ",
33                CPLD_READ(hw_ver), CPLD_READ(sw_ver));
34
35 #ifdef CONFIG_SDCARD
36         puts("SD/MMC\n");
37 #elif CONFIG_SPIFLASH
38         puts("SPI\n");
39 #else
40         u8 reg;
41
42         reg = CPLD_READ(flash_csr);
43
44         if (reg & CPLD_BOOT_SEL) {
45                 puts("NAND\n");
46         } else {
47                 reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
48                 printf("NOR vBank%d\n", reg);
49         }
50 #endif
51
52         puts("SERDES Reference Clocks:\n");
53         printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
54         printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[0], freq[0]);
55
56         return 0;
57 }
58
59 int board_early_init_r(void)
60 {
61         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
62         int flash_esel = find_tlb_idx((void *)flashbase, 1);
63         /*
64          * Remap Boot flash + PROMJET region to caching-inhibited
65          * so that flash can be erased properly.
66          */
67
68         /* Flush d-cache and invalidate i-cache of any FLASH data */
69         flush_dcache();
70         invalidate_icache();
71         if (flash_esel == -1) {
72                 /* very unlikely unless something is messed up */
73                 puts("Error: Could not find TLB for FLASH BASE\n");
74                 flash_esel = 2; /* give our best effort to continue */
75         } else {
76                 /* invalidate existing TLB entry for flash + promjet */
77                 disable_tlb(flash_esel);
78         }
79
80         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
81                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
82                 0, flash_esel, BOOKE_PAGESZ_256M, 1);
83
84         /*
85          * Adjust core voltage according to voltage ID
86          * This function changes I2C mux to channel 2.
87          */
88         if (adjust_vdd(0))
89                 printf("Warning: Adjusting core voltage failed.\n");
90         return 0;
91 }
92
93 unsigned long get_board_sys_clk(void)
94 {
95         return CONFIG_SYS_CLK_FREQ;
96 }
97
98 unsigned long get_board_ddr_clk(void)
99 {
100         return CONFIG_DDR_CLK_FREQ;
101 }
102
103 int misc_init_r(void)
104 {
105         u8 reg;
106
107         /* Reset CS4315 PHY */
108         reg = CPLD_READ(reset_ctl);
109         reg |= CPLD_RSTCON_EDC_RST;
110         CPLD_WRITE(reset_ctl, reg);
111
112         return 0;
113 }
114
115 int ft_board_setup(void *blob, bd_t *bd)
116 {
117         phys_addr_t base;
118         phys_size_t size;
119
120         ft_cpu_setup(blob, bd);
121
122         base = env_get_bootm_low();
123         size = env_get_bootm_size();
124
125         fdt_fixup_memory(blob, (u64)base, (u64)size);
126
127 #ifdef CONFIG_PCI
128         pci_of_setup(blob, bd);
129 #endif
130
131         fdt_fixup_liodn(blob);
132         fsl_fdt_fixup_dr_usb(blob, bd);
133
134 #ifdef CONFIG_SYS_DPAA_FMAN
135         fdt_fixup_fman_ethernet(blob);
136         fdt_fixup_board_enet(blob);
137 #endif
138
139         return 0;
140 }