1 T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC.
2 It can work in two mode: standalone mode and PCIe endpoint mode.
6 The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
7 Architecture processor cores with high-performance datapath acceleration
8 logic and network and peripheral bus interfaces required for networking,
9 telecom/datacom, wireless infrastructure, and mil/aerospace applications.
11 T2080 includes the following functions and features:
12 - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
13 - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
14 - Hierarchical interconnect fabric
15 - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
16 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
17 - 16 SerDes lanes up to 10.3125 GHz
18 - 8 Ethernet interfaces, supporting combinations of the following:
19 - Up to four 10 Gbps Ethernet MACs
20 - Up to eight 1 Gbps Ethernet MACs
21 - Up to four 2.5 Gbps Ethernet MACs
22 - High-speed peripheral interfaces
23 - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
24 - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
25 - Additional peripheral interfaces
26 - Two serial ATA (SATA 2.0) controllers
27 - Two high-speed USB 2.0 controllers with integrated PHY
28 - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
29 - Enhanced serial peripheral interface (eSPI)
30 - Four I2C controllers
31 - Four 2-pin UARTs or two 4-pin UARTs
32 - Integrated Flash Controller supporting NAND and NOR flash
33 - Three eight-channel DMA engines
34 - Support for hardware virtualization and partitioning enforcement
35 - QorIQ Platform's Trust Architecture 2.0
39 The T2080RDB User Guide is available on the web at
40 https://www.nxp.com/docs/en/user-guide/T2080RDBPCUG.pdf
42 Differences between T2080 and T2081
43 -----------------------------------
45 1G Ethernet numbers: 8 6
46 10G Ethernet numbers: 4 2
48 Serial RapidIO,RMan: 2 no
51 SoC Package: 896-pins 780-pins
54 T2080PCIe-RDB board Overview
55 ----------------------------
56 - SERDES Configuration
57 - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10)
58 - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2)
59 - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3)
60 - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2)
61 - SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2)
62 - SerDes-2 Lane G-H: to SATA1 & SATA2
64 - Two on-board 10M/100M/1G RGMII ethernet ports
65 - Two on-board 10Gbps XFI fiber ports
66 - Two on-board 10Gbps Base-T copper ports
68 - Supports 72bit 4GB DDR3-LP SODIMM
70 - One PCIe x4 gold-finger
71 - One PCIe x4 connector
72 - One PCIe x2 end-point device (C293 Crypto co-processor)
74 - NOR: 128MB 16-bit NOR Flash
75 - NAND: 1GB 8-bit NAND flash
76 - CPLD: for system controlling with programable header on-board
78 - Two SATA 2.0 onnectors on-board
80 - Supports two USB 2.0 ports with integrated PHYs
81 - Two type A ports with 5V@1.5A per port.
83 - one TF-card connector on-board
85 - On-board 64MB SPI flash
93 Start Address End Address Description Size
94 0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
95 0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
96 0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
97 0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB
98 0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
99 0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
100 0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
101 0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
102 0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
103 0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
104 0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
105 0xC_4000_0000 0xC_4FFF_FFFF PCI Express 4 Mem Space 256MB
106 0xC_3000_0000 0xC_3FFF_FFFF PCI Express 3 Mem Space 256MB
107 0xC_2000_0000 0xC_2FFF_FFFF PCI Express 2 Mem Space 256MB
108 0xC_0000_0000 0xC_1FFF_FFFF PCI Express 1 Mem Space 512MB
109 0x0_0000_0000 0x0_ffff_ffff DDR 4GB
112 128M NOR Flash memory Map
113 -------------------------
114 Start Address End Address Definition Max size
115 0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB
116 0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB
117 0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
118 0xEFE00000 0xEFE3FFFF PHY CS4315 firmware 256KB
119 0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
120 0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
121 0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
122 0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
123 0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB
124 0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB
125 0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
126 0xEBE00000 0xEBE3FFFF PHY CS4315 firmware (alt bank) 256KB
127 0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
128 0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
129 0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
130 0xE8000000 0xE801FFFF RCW (current bank) 128KB
133 T2080PCIe-RDB Ethernet Port Map
134 -------------------------------
135 Label In Uboot In Linux FMan Address Comments PHY
136 ETH0 FM1@GTEC1 fm1-mac9 0xfe4f0000 10G SFP+ (CS4315)
137 ETH1 FM1@GTEC2 fm1-mac10 0xfe4f2000 10G SFP+ (CS4315)
138 ETH2 FM1@GTEC3 fm1-mac1 0xfe4e0000 10G Base-T (AQ1202)
139 ETH3 FM1@GTEC4 fm1-mac2 0xfe4e2000 10G Base-T (AQ1202)
140 ETH4 FM1@DTSEC3 fm1-mac3 0xfe4e4000 1G RGMII (RTL8211E)
141 ETH5 FM1@DTSEC4 fm1-mac4 0xfe4e6000 1G RGMII (RTL8211E)
144 T2080PCIe-RDB Default DIP-Switch setting
145 ----------------------------------------
146 SW1[1:8] = '00010011'
147 SW2[1:8] = '10111111'
148 SW3[1:8] = '11100001'
150 Software configurations and board settings
151 ------------------------------------------
153 a. build NOR boot image
154 $ make T2080RDB_config
156 b. program u-boot.bin image to NOR flash
157 => tftp 1000000 u-boot.bin
158 => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
159 set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
161 Switching between default bank and alternate bank on NOR flash
162 To change boot source to vbank4:
163 via software: run command 'cpld reset altbank' in U-Boot.
164 via DIP-switch: set SW3[5:7] = '100'
166 To change boot source to vbank0:
167 via software: run command 'cpld reset' in U-Boot.
168 via DIP-Switch: set SW3[5:7] = '000'
171 a. build PBL image for NAND boot
172 $ make T2080RDB_NAND_config
174 b. program u-boot-with-spl-pbl.bin to NAND flash
175 => tftp 1000000 u-boot-with-spl-pbl.bin
176 => nand erase 0 d0000
177 => nand write 1000000 0 $filesize
178 set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
181 a. build PBL image for SPI boot
182 $ make T2080RDB_SPIFLASH_config
184 b. program u-boot-with-spl-pbl.bin to SPI flash
185 => tftp 1000000 u-boot-with-spl-pbl.bin
188 => sf write 1000000 0 $filesize
189 set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
192 a. build PBL image for SD boot
193 $ make T2080RDB_SDCARD_config
195 b. program u-boot-with-spl-pbl.bin to micro-SD/TF card
196 => tftp 1000000 u-boot-with-spl-pbl.bin
197 => mmc write 1000000 8 0x800
198 set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
201 2-stage NAND/SPI/SD boot loader
202 -------------------------------
203 PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
204 SPL further initializes DDR using SPD and environment variables
205 and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR.
206 Finally SPL transers control to U-Boot for futher booting.
208 SPL has following features:
209 - Executes within 256K
210 - No relocation required
212 Run time view of SPL framework
213 -------------------------------------------------
215 -------------------------------------------------
216 |SecureBoot header | 0xFFFC0000 (32KB) |
217 -------------------------------------------------
218 |GD, BD | 0xFFFC8000 (4KB) |
219 -------------------------------------------------
220 |ENV | 0xFFFC9000 (8KB) |
221 -------------------------------------------------
222 |HEAP | 0xFFFCB000 (50KB) |
223 -------------------------------------------------
224 |STACK | 0xFFFD8000 (22KB) |
225 -------------------------------------------------
226 |U-Boot SPL | 0xFFFD8000 (160KB) |
227 -------------------------------------------------
229 NAND Flash memory Map on T2080RDB
230 --------------------------------------------------------------
231 Start End Definition Size
232 0x000000 0x0FFFFF U-Boot img 1MB (2 blocks)
233 0x100000 0x17FFFF U-Boot env 512KB (1 block)
234 0x180000 0x1FFFFF FMAN ucode 512KB (1 block)
235 0x200000 0x27FFFF CS4315 ucode 512KB (1 block)
238 Micro SD Card memory Map on T2080RDB
239 ----------------------------------------------------
240 Block #blocks Definition Size
241 0x008 2048 U-Boot img 1MB
242 0x800 0016 U-Boot env 8KB
243 0x820 0128 FMAN ucode 64KB
244 0x8a0 0512 CS4315 ucode 256KB
247 SPI Flash memory Map on T2080RDB
248 ----------------------------------------------------
249 Start End Definition Size
250 0x000000 0x0FFFFF U-Boot img 1MB
251 0x100000 0x101FFF U-Boot env 8KB
252 0x110000 0x11FFFF FMAN ucode 64KB
253 0x120000 0x15FFFF CS4315 ucode 256KB
256 How to update the ucode of Cortina CS4315/CS4340 10G PHY
257 --------------------------------------------------------
258 => tftp 1000000 CS4315-CS4340-PHY-ucode.txt
259 => pro off all;era 0xefe00000 0xefefffff;cp.b 1000000 0xefe00000 $filesize
262 How to update the ucode of Freescale FMAN
263 -----------------------------------------
264 => tftp 1000000 fsl_fman_ucode_t2080_r1.0.bin
265 => pro off all;erase 0xeff00000 0xeff1ffff;cp 1000000 0xeff00000 $filesize
268 For more details, please refer to T2080PCIe-RDB User Guide and access
269 website www.freescale.com and Freescale QorIQ SDK Infocenter document.
271 Device tree support and how to enable it for different configs
272 --------------------------------------------------------------
273 Device tree support is available for t2080rdb for below mentioned boot,
279 To enable device tree support for other boot, below configs need to be
280 enabled in relative defconfig file,
281 1. CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" (Change default device tree name if required)
283 3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
284 CONFIG_RESET_VECTOR_ADDRESS - 0xffc
286 If device tree support is enabled in defconfig,
287 1. use 'u-boot-with-dtb.bin' for NOR boot.
288 2. use 'u-boot-with-spl-pbl.bin' for other boot.