board/freescale/t208xqds/t208xqds.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2009-2013 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <env.h>
  10 #include <fdt_support.h>
  11 #include <i2c.h>
  12 #include <image.h>
  13 #include <init.h>
  14 #include <log.h>
  15 #include <netdev.h>
  16 #include <linux/compiler.h>
  17 #include <asm/mmu.h>
  18 #include <asm/processor.h>
  19 #include <asm/immap_85xx.h>
  20 #include <asm/fsl_law.h>
  21 #include <asm/fsl_serdes.h>
  22 #include <asm/fsl_liodn.h>
  23 #include <fm_eth.h>
  24
  25 #include "../common/qixis.h"
  26 #include "../common/vsc3316_3308.h"
  27 #include "../common/vid.h"
  28 #include "t208xqds.h"
  29 #include "t208xqds_qixis.h"
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 int checkboard(void)
  34 {
  35         char buf[64];
  36         u8 sw;
  37         struct cpu_type *cpu = gd->arch.cpu;
  38         static const char *freq[4] = {
  39                 "100.00MHZ(from 8T49N222A)", "125.00MHz",
  40                 "156.25MHZ", "100.00MHz"
  41         };
  42
  43         printf("Board: %sQDS, ", cpu->name);
  44         sw = QIXIS_READ(arch);
  45         printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
  46         printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
  47
  48 #ifdef CONFIG_SDCARD
  49         puts("SD/MMC\n");
  50 #elif CONFIG_SPIFLASH
  51         puts("SPI\n");
  52 #else
  53         sw = QIXIS_READ(brdcfg[0]);
  54         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  55
  56         if (sw < 0x8)
  57                 printf("vBank%d\n", sw);
  58         else if (sw == 0x8)
  59                 puts("Promjet\n");
  60         else if (sw == 0x9)
  61                 puts("NAND\n");
  62         else
  63                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  64 #endif
  65
  66         printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver),
  67                qixis_read_tag(buf), (int)qixis_read_minor());
  68         /* the timestamp string contains "\n" at the end */
  69         printf(" on %s", qixis_read_time(buf));
  70
  71         puts("SERDES Reference Clocks:\n");
  72         sw = QIXIS_READ(brdcfg[2]);
  73         printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6],
  74                freq[(sw >> 4) & 0x3]);
  75         printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2],
  76                freq[sw & 0x3]);
  77
  78         return 0;
  79 }
  80
  81 int select_i2c_ch_pca9547(u8 ch, int bus_num)
  82 {
  83         int ret;
  84
  85 #ifdef CONFIG_DM_I2C
  86         struct udevice *dev;
  87
  88         ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
  89         if (ret) {
  90                 printf("%s: Cannot find udev for a bus %d\n", __func__,
  91                        bus_num);
  92                 return ret;
  93         }
  94         ret = dm_i2c_write(dev, 0, &ch, 1);
  95 #else
  96         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  97 #endif
  98         if (ret) {
  99                 puts("PCA: failed to select proper channel\n");
 100                 return ret;
 101         }
 102
 103         return 0;
 104 }
 105
 106 int i2c_multiplexer_select_vid_channel(u8 channel)
 107 {
 108         return select_i2c_ch_pca9547(channel, 0);
 109 }
 110
 111 int brd_mux_lane_to_slot(void)
 112 {
 113         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 114         u32 srds_prtcl_s1;
 115
 116         srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
 117                                 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 118         srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 119 #if defined(CONFIG_TARGET_T2080QDS)
 120         u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
 121                                 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 122         srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 123 #endif
 124
 125         switch (srds_prtcl_s1) {
 126         case 0:
 127                 /* SerDes1 is not enabled */
 128                 break;
 129 #if defined(CONFIG_TARGET_T2080QDS)
 130         case 0x1b:
 131         case 0x1c:
 132         case 0xa2:
 133                 /* SD1(A:D) => SLOT3 SGMII
 134                  * SD1(G:H) => SLOT1 SGMII
 135                  */
 136                 QIXIS_WRITE(brdcfg[12], 0x1a);
 137                 break;
 138         case 0x94:
 139         case 0x95:
 140                 /* SD1(A:B) => SLOT3 SGMII@1.25bps
 141                  * SD1(C:D) => SFP Module, SGMII@3.125bps
 142                  * SD1(E:H) => SLOT1 SGMII@1.25bps
 143                  */
 144         case 0x96:
 145                 /* SD1(A:B) => SLOT3 SGMII@1.25bps
 146                  * SD1(C)   => SFP Module, SGMII@3.125bps
 147                  * SD1(D)   => SFP Module, SGMII@1.25bps
 148                  * SD1(E:H) => SLOT1 PCIe4 x4
 149                  */
 150                 QIXIS_WRITE(brdcfg[12], 0x3a);
 151                 break;
 152         case 0x50:
 153         case 0x51:
 154                 /* SD1(A:D) => SLOT3 XAUI
 155                  * SD1(E)   => SLOT1 PCIe4
 156                  * SD1(F:H) => SLOT2 SGMII
 157                  */
 158                 QIXIS_WRITE(brdcfg[12], 0x15);
 159                 break;
 160         case 0x66:
 161         case 0x67:
 162                 /* SD1(A:D) => XFI cage
 163                  * SD1(E:H) => SLOT1 PCIe4
 164                  */
 165                 QIXIS_WRITE(brdcfg[12], 0xfe);
 166                 break;
 167         case 0x6a:
 168         case 0x6b:
 169                 /* SD1(A:D) => XFI cage
 170                  * SD1(E)   => SLOT1 PCIe4
 171                  * SD1(F:H) => SLOT2 SGMII
 172                  */
 173                 QIXIS_WRITE(brdcfg[12], 0xf1);
 174                 break;
 175         case 0x6c:
 176         case 0x6d:
 177                 /* SD1(A:B) => XFI cage
 178                  * SD1(C:D) => SLOT3 SGMII
 179                  * SD1(E:H) => SLOT1 PCIe4
 180                  */
 181                 QIXIS_WRITE(brdcfg[12], 0xda);
 182                 break;
 183         case 0x6e:
 184                 /* SD1(A:B) => SFP Module, XFI
 185                  * SD1(C:D) => SLOT3 SGMII
 186                  * SD1(E:F) => SLOT1 PCIe4 x2
 187                  * SD1(G:H) => SLOT2 SGMII
 188                  */
 189                 QIXIS_WRITE(brdcfg[12], 0xd9);
 190                 break;
 191         case 0xda:
 192                 /* SD1(A:H) => SLOT3 PCIe3 x8
 193                  */
 194                  QIXIS_WRITE(brdcfg[12], 0x0);
 195                  break;
 196         case 0xc8:
 197                 /* SD1(A)   => SLOT3 PCIe3 x1
 198                  * SD1(B)   => SFP Module, SGMII@1.25bps
 199                  * SD1(C:D) => SFP Module, SGMII@3.125bps
 200                  * SD1(E:F) => SLOT1 PCIe4 x2
 201                  * SD1(G:H) => SLOT2 SGMII
 202                  */
 203                  QIXIS_WRITE(brdcfg[12], 0x79);
 204                  break;
 205         case 0xab:
 206                 /* SD1(A:D) => SLOT3 PCIe3 x4
 207                  * SD1(E:H) => SLOT1 PCIe4 x4
 208                  */
 209                  QIXIS_WRITE(brdcfg[12], 0x1a);
 210                  break;
 211 #elif defined(CONFIG_TARGET_T2081QDS)
 212         case 0x50:
 213         case 0x51:
 214                 /* SD1(A:D) => SLOT2 XAUI
 215                  * SD1(E)   => SLOT1 PCIe4 x1
 216                  * SD1(F:H) => SLOT3 SGMII
 217                  */
 218                 QIXIS_WRITE(brdcfg[12], 0x98);
 219                 QIXIS_WRITE(brdcfg[13], 0x70);
 220                 break;
 221         case 0x6a:
 222         case 0x6b:
 223                 /* SD1(A:D) => XFI SFP Module
 224                  * SD1(E)   => SLOT1 PCIe4 x1
 225                  * SD1(F:H) => SLOT3 SGMII
 226                  */
 227                 QIXIS_WRITE(brdcfg[12], 0x80);
 228                 QIXIS_WRITE(brdcfg[13], 0x70);
 229                 break;
 230         case 0x6c:
 231         case 0x6d:
 232                 /* SD1(A:B) => XFI SFP Module
 233                  * SD1(C:D) => SLOT2 SGMII
 234                  * SD1(E:H) => SLOT1 PCIe4 x4
 235                  */
 236                 QIXIS_WRITE(brdcfg[12], 0xe8);
 237                 QIXIS_WRITE(brdcfg[13], 0x0);
 238                 break;
 239         case 0xaa:
 240         case 0xab:
 241                 /* SD1(A:D) => SLOT2 PCIe3 x4
 242                  * SD1(F:H) => SLOT1 SGMI4 x4
 243                  */
 244                 QIXIS_WRITE(brdcfg[12], 0xf8);
 245                 QIXIS_WRITE(brdcfg[13], 0x0);
 246                 break;
 247         case 0xca:
 248         case 0xcb:
 249                 /* SD1(A)   => SLOT2 PCIe3 x1
 250                  * SD1(B)   => SLOT7 SGMII
 251                  * SD1(C)   => SLOT6 SGMII
 252                  * SD1(D)   => SLOT5 SGMII
 253                  * SD1(E)   => SLOT1 PCIe4 x1
 254                  * SD1(F:H) => SLOT3 SGMII
 255                  */
 256                 QIXIS_WRITE(brdcfg[12], 0x80);
 257                 QIXIS_WRITE(brdcfg[13], 0x70);
 258                 break;
 259         case 0xde:
 260         case 0xdf:
 261                 /* SD1(A:D) => SLOT2 PCIe3 x4
 262                  * SD1(E)   => SLOT1 PCIe4 x1
 263                  * SD1(F)   => SLOT4 PCIe1 x1
 264                  * SD1(G)   => SLOT3 PCIe2 x1
 265                  * SD1(H)   => SLOT7 SGMII
 266                  */
 267                 QIXIS_WRITE(brdcfg[12], 0x98);
 268                 QIXIS_WRITE(brdcfg[13], 0x25);
 269                 break;
 270         case 0xf2:
 271                 /* SD1(A)   => SLOT2 PCIe3 x1
 272                  * SD1(B:D) => SLOT7 SGMII
 273                  * SD1(E)   => SLOT1 PCIe4 x1
 274                  * SD1(F)   => SLOT4 PCIe1 x1
 275                  * SD1(G)   => SLOT3 PCIe2 x1
 276                  * SD1(H)   => SLOT7 SGMII
 277                  */
 278                 QIXIS_WRITE(brdcfg[12], 0x81);
 279                 QIXIS_WRITE(brdcfg[13], 0xa5);
 280                 break;
 281 #endif
 282         default:
 283                 printf("WARNING: unsupported for SerDes1 Protocol %d\n",
 284                        srds_prtcl_s1);
 285                 return -1;
 286         }
 287
 288 #ifdef CONFIG_TARGET_T2080QDS
 289         switch (srds_prtcl_s2) {
 290         case 0:
 291                 /* SerDes2 is not enabled */
 292                 break;
 293         case 0x01:
 294         case 0x02:
 295                 /* SD2(A:H) => SLOT4 PCIe1 */
 296                 QIXIS_WRITE(brdcfg[13], 0x10);
 297                 break;
 298         case 0x15:
 299         case 0x16:
 300                 /*
 301                  * SD2(A:D) => SLOT4 PCIe1
 302                  * SD2(E:F) => SLOT5 PCIe2
 303                  * SD2(G:H) => SATA1,SATA2
 304                  */
 305                 QIXIS_WRITE(brdcfg[13], 0xb0);
 306                 break;
 307         case 0x18:
 308                 /*
 309                  * SD2(A:D) => SLOT4 PCIe1
 310                  * SD2(E:F) => SLOT5 Aurora
 311                  * SD2(G:H) => SATA1,SATA2
 312                  */
 313                 QIXIS_WRITE(brdcfg[13], 0x78);
 314                 break;
 315         case 0x1f:
 316                 /*
 317                  * SD2(A:D) => SLOT4 PCIe1
 318                  * SD2(E:H) => SLOT5 PCIe2
 319                  */
 320                 QIXIS_WRITE(brdcfg[13], 0xa0);
 321                 break;
 322         case 0x29:
 323         case 0x2d:
 324         case 0x2e:
 325                 /*
 326                  * SD2(A:D) => SLOT4 SRIO2
 327                  * SD2(E:H) => SLOT5 SRIO1
 328                  */
 329                 QIXIS_WRITE(brdcfg[13], 0xa0);
 330                 break;
 331         case 0x36:
 332                 /*
 333                  * SD2(A:D) => SLOT4 SRIO2
 334                  * SD2(E:F) => Aurora
 335                  * SD2(G:H) => SATA1,SATA2
 336                  */
 337                 QIXIS_WRITE(brdcfg[13], 0x78);
 338                 break;
 339         default:
 340                 printf("WARNING: unsupported for SerDes2 Protocol %d\n",
 341                        srds_prtcl_s2);
 342                 return -1;
 343         }
 344 #endif
 345         return 0;
 346 }
 347
 348 static void esdhc_adapter_card_ident(void)
 349 {
 350         u8 card_id, value;
 351
 352         card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
 353
 354         switch (card_id) {
 355         case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
 356                 value = QIXIS_READ(brdcfg[5]);
 357                 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
 358                 QIXIS_WRITE(brdcfg[5], value);
 359                 break;
 360         case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
 361                 value = QIXIS_READ(pwr_ctl[1]);
 362                 value |= QIXIS_EVDD_BY_SDHC_VS;
 363                 QIXIS_WRITE(pwr_ctl[1], value);
 364                 break;
 365         case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
 366                 value = QIXIS_READ(brdcfg[5]);
 367                 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
 368                 QIXIS_WRITE(brdcfg[5], value);
 369                 break;
 370         default:
 371                 break;
 372         }
 373 }
 374
 375 int board_early_init_r(void)
 376 {
 377         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 378         int flash_esel = find_tlb_idx((void *)flashbase, 1);
 379
 380         /*
 381          * Remap Boot flash + PROMJET region to caching-inhibited
 382          * so that flash can be erased properly.
 383          */
 384
 385         /* Flush d-cache and invalidate i-cache of any FLASH data */
 386         flush_dcache();
 387         invalidate_icache();
 388
 389         if (flash_esel == -1) {
 390                 /* very unlikely unless something is messed up */
 391                 puts("Error: Could not find TLB for FLASH BASE\n");
 392                 flash_esel = 2; /* give our best effort to continue */
 393         } else {
 394                 /* invalidate existing TLB entry for flash + promjet */
 395                 disable_tlb(flash_esel);
 396         }
 397
 398         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 399                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 400                 0, flash_esel, BOOKE_PAGESZ_256M, 1);
 401
 402         /* Disable remote I2C connection to qixis fpga */
 403         QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
 404
 405         /*
 406          * Adjust core voltage according to voltage ID
 407          * This function changes I2C mux to channel 2.
 408          */
 409         if (adjust_vdd(0))
 410                 printf("Warning: Adjusting core voltage failed.\n");
 411
 412         brd_mux_lane_to_slot();
 413         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 414         esdhc_adapter_card_ident();
 415         return 0;
 416 }
 417
 418 unsigned long get_board_sys_clk(void)
 419 {
 420         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 421 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
 422         /* use accurate clock measurement */
 423         int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
 424         int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
 425         u32 val;
 426
 427         val =  freq * base;
 428         if (val) {
 429                 debug("SYS Clock measurement is: %d\n", val);
 430                 return val;
 431         } else {
 432                 printf("Warning: SYS clock measurement is invalid, ");
 433                 printf("using value from brdcfg1.\n");
 434         }
 435 #endif
 436
 437         switch (sysclk_conf & 0x0F) {
 438         case QIXIS_SYSCLK_83:
 439                 return 83333333;
 440         case QIXIS_SYSCLK_100:
 441                 return 100000000;
 442         case QIXIS_SYSCLK_125:
 443                 return 125000000;
 444         case QIXIS_SYSCLK_133:
 445                 return 133333333;
 446         case QIXIS_SYSCLK_150:
 447                 return 150000000;
 448         case QIXIS_SYSCLK_160:
 449                 return 160000000;
 450         case QIXIS_SYSCLK_166:
 451                 return 166666666;
 452         }
 453         return 66666666;
 454 }
 455
 456 unsigned long get_board_ddr_clk(void)
 457 {
 458         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 459 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
 460         /* use accurate clock measurement */
 461         int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
 462         int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
 463         u32 val;
 464
 465         val =  freq * base;
 466         if (val) {
 467                 debug("DDR Clock measurement is: %d\n", val);
 468                 return val;
 469         } else {
 470                 printf("Warning: DDR clock measurement is invalid, ");
 471                 printf("using value from brdcfg1.\n");
 472         }
 473 #endif
 474
 475         switch ((ddrclk_conf & 0x30) >> 4) {
 476         case QIXIS_DDRCLK_100:
 477                 return 100000000;
 478         case QIXIS_DDRCLK_125:
 479                 return 125000000;
 480         case QIXIS_DDRCLK_133:
 481                 return 133333333;
 482         }
 483         return 66666666;
 484 }
 485
 486 int misc_init_r(void)
 487 {
 488         return 0;
 489 }
 490
 491 int ft_board_setup(void *blob, struct bd_info *bd)
 492 {
 493         phys_addr_t base;
 494         phys_size_t size;
 495
 496         ft_cpu_setup(blob, bd);
 497
 498         base = env_get_bootm_low();
 499         size = env_get_bootm_size();
 500
 501         fdt_fixup_memory(blob, (u64)base, (u64)size);
 502
 503 #ifdef CONFIG_PCI
 504         pci_of_setup(blob, bd);
 505 #endif
 506
 507         fdt_fixup_liodn(blob);
 508         fsl_fdt_fixup_dr_usb(blob, bd);
 509
 510 #ifdef CONFIG_SYS_DPAA_FMAN
 511 #ifndef CONFIG_DM_ETH
 512         fdt_fixup_fman_ethernet(blob);
 513 #endif
 514         fdt_fixup_board_enet(blob);
 515 #endif
 516
 517         return 0;
 518 }