1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2013 Freescale Semiconductor, Inc.
10 #include <fdt_support.h>
14 #include <linux/compiler.h>
16 #include <asm/processor.h>
17 #include <asm/immap_85xx.h>
18 #include <asm/fsl_law.h>
19 #include <asm/fsl_serdes.h>
20 #include <asm/fsl_liodn.h>
23 #include "../common/qixis.h"
24 #include "../common/vsc3316_3308.h"
25 #include "../common/vid.h"
27 #include "t208xqds_qixis.h"
29 DECLARE_GLOBAL_DATA_PTR;
35 struct cpu_type *cpu = gd->arch.cpu;
36 static const char *freq[4] = {
37 "100.00MHZ(from 8T49N222A)", "125.00MHz",
38 "156.25MHZ", "100.00MHz"
41 printf("Board: %sQDS, ", cpu->name);
42 sw = QIXIS_READ(arch);
43 printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
44 printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
51 sw = QIXIS_READ(brdcfg[0]);
52 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
55 printf("vBank%d\n", sw);
61 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
64 printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver),
65 qixis_read_tag(buf), (int)qixis_read_minor());
66 /* the timestamp string contains "\n" at the end */
67 printf(" on %s", qixis_read_time(buf));
69 puts("SERDES Reference Clocks:\n");
70 sw = QIXIS_READ(brdcfg[2]);
71 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6],
72 freq[(sw >> 4) & 0x3]);
73 printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2],
79 int select_i2c_ch_pca9547(u8 ch, int bus_num)
86 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
88 printf("%s: Cannot find udev for a bus %d\n", __func__,
92 ret = dm_i2c_write(dev, 0, &ch, 1);
94 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
97 puts("PCA: failed to select proper channel\n");
104 int i2c_multiplexer_select_vid_channel(u8 channel)
106 return select_i2c_ch_pca9547(channel, 0);
109 int brd_mux_lane_to_slot(void)
111 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
114 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
115 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
116 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
117 #if defined(CONFIG_TARGET_T2080QDS)
118 u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
119 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
120 srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
123 switch (srds_prtcl_s1) {
125 /* SerDes1 is not enabled */
127 #if defined(CONFIG_TARGET_T2080QDS)
131 /* SD1(A:D) => SLOT3 SGMII
132 * SD1(G:H) => SLOT1 SGMII
134 QIXIS_WRITE(brdcfg[12], 0x1a);
138 /* SD1(A:B) => SLOT3 SGMII@1.25bps
139 * SD1(C:D) => SFP Module, SGMII@3.125bps
140 * SD1(E:H) => SLOT1 SGMII@1.25bps
143 /* SD1(A:B) => SLOT3 SGMII@1.25bps
144 * SD1(C) => SFP Module, SGMII@3.125bps
145 * SD1(D) => SFP Module, SGMII@1.25bps
146 * SD1(E:H) => SLOT1 PCIe4 x4
148 QIXIS_WRITE(brdcfg[12], 0x3a);
152 /* SD1(A:D) => SLOT3 XAUI
153 * SD1(E) => SLOT1 PCIe4
154 * SD1(F:H) => SLOT2 SGMII
156 QIXIS_WRITE(brdcfg[12], 0x15);
160 /* SD1(A:D) => XFI cage
161 * SD1(E:H) => SLOT1 PCIe4
163 QIXIS_WRITE(brdcfg[12], 0xfe);
167 /* SD1(A:D) => XFI cage
168 * SD1(E) => SLOT1 PCIe4
169 * SD1(F:H) => SLOT2 SGMII
171 QIXIS_WRITE(brdcfg[12], 0xf1);
175 /* SD1(A:B) => XFI cage
176 * SD1(C:D) => SLOT3 SGMII
177 * SD1(E:H) => SLOT1 PCIe4
179 QIXIS_WRITE(brdcfg[12], 0xda);
182 /* SD1(A:B) => SFP Module, XFI
183 * SD1(C:D) => SLOT3 SGMII
184 * SD1(E:F) => SLOT1 PCIe4 x2
185 * SD1(G:H) => SLOT2 SGMII
187 QIXIS_WRITE(brdcfg[12], 0xd9);
190 /* SD1(A:H) => SLOT3 PCIe3 x8
192 QIXIS_WRITE(brdcfg[12], 0x0);
195 /* SD1(A) => SLOT3 PCIe3 x1
196 * SD1(B) => SFP Module, SGMII@1.25bps
197 * SD1(C:D) => SFP Module, SGMII@3.125bps
198 * SD1(E:F) => SLOT1 PCIe4 x2
199 * SD1(G:H) => SLOT2 SGMII
201 QIXIS_WRITE(brdcfg[12], 0x79);
204 /* SD1(A:D) => SLOT3 PCIe3 x4
205 * SD1(E:H) => SLOT1 PCIe4 x4
207 QIXIS_WRITE(brdcfg[12], 0x1a);
209 #elif defined(CONFIG_TARGET_T2081QDS)
212 /* SD1(A:D) => SLOT2 XAUI
213 * SD1(E) => SLOT1 PCIe4 x1
214 * SD1(F:H) => SLOT3 SGMII
216 QIXIS_WRITE(brdcfg[12], 0x98);
217 QIXIS_WRITE(brdcfg[13], 0x70);
221 /* SD1(A:D) => XFI SFP Module
222 * SD1(E) => SLOT1 PCIe4 x1
223 * SD1(F:H) => SLOT3 SGMII
225 QIXIS_WRITE(brdcfg[12], 0x80);
226 QIXIS_WRITE(brdcfg[13], 0x70);
230 /* SD1(A:B) => XFI SFP Module
231 * SD1(C:D) => SLOT2 SGMII
232 * SD1(E:H) => SLOT1 PCIe4 x4
234 QIXIS_WRITE(brdcfg[12], 0xe8);
235 QIXIS_WRITE(brdcfg[13], 0x0);
239 /* SD1(A:D) => SLOT2 PCIe3 x4
240 * SD1(F:H) => SLOT1 SGMI4 x4
242 QIXIS_WRITE(brdcfg[12], 0xf8);
243 QIXIS_WRITE(brdcfg[13], 0x0);
247 /* SD1(A) => SLOT2 PCIe3 x1
248 * SD1(B) => SLOT7 SGMII
249 * SD1(C) => SLOT6 SGMII
250 * SD1(D) => SLOT5 SGMII
251 * SD1(E) => SLOT1 PCIe4 x1
252 * SD1(F:H) => SLOT3 SGMII
254 QIXIS_WRITE(brdcfg[12], 0x80);
255 QIXIS_WRITE(brdcfg[13], 0x70);
259 /* SD1(A:D) => SLOT2 PCIe3 x4
260 * SD1(E) => SLOT1 PCIe4 x1
261 * SD1(F) => SLOT4 PCIe1 x1
262 * SD1(G) => SLOT3 PCIe2 x1
263 * SD1(H) => SLOT7 SGMII
265 QIXIS_WRITE(brdcfg[12], 0x98);
266 QIXIS_WRITE(brdcfg[13], 0x25);
269 /* SD1(A) => SLOT2 PCIe3 x1
270 * SD1(B:D) => SLOT7 SGMII
271 * SD1(E) => SLOT1 PCIe4 x1
272 * SD1(F) => SLOT4 PCIe1 x1
273 * SD1(G) => SLOT3 PCIe2 x1
274 * SD1(H) => SLOT7 SGMII
276 QIXIS_WRITE(brdcfg[12], 0x81);
277 QIXIS_WRITE(brdcfg[13], 0xa5);
281 printf("WARNING: unsupported for SerDes1 Protocol %d\n",
286 #ifdef CONFIG_TARGET_T2080QDS
287 switch (srds_prtcl_s2) {
289 /* SerDes2 is not enabled */
293 /* SD2(A:H) => SLOT4 PCIe1 */
294 QIXIS_WRITE(brdcfg[13], 0x10);
299 * SD2(A:D) => SLOT4 PCIe1
300 * SD2(E:F) => SLOT5 PCIe2
301 * SD2(G:H) => SATA1,SATA2
303 QIXIS_WRITE(brdcfg[13], 0xb0);
307 * SD2(A:D) => SLOT4 PCIe1
308 * SD2(E:F) => SLOT5 Aurora
309 * SD2(G:H) => SATA1,SATA2
311 QIXIS_WRITE(brdcfg[13], 0x78);
315 * SD2(A:D) => SLOT4 PCIe1
316 * SD2(E:H) => SLOT5 PCIe2
318 QIXIS_WRITE(brdcfg[13], 0xa0);
324 * SD2(A:D) => SLOT4 SRIO2
325 * SD2(E:H) => SLOT5 SRIO1
327 QIXIS_WRITE(brdcfg[13], 0xa0);
331 * SD2(A:D) => SLOT4 SRIO2
333 * SD2(G:H) => SATA1,SATA2
335 QIXIS_WRITE(brdcfg[13], 0x78);
338 printf("WARNING: unsupported for SerDes2 Protocol %d\n",
346 int board_early_init_r(void)
348 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
349 int flash_esel = find_tlb_idx((void *)flashbase, 1);
352 * Remap Boot flash + PROMJET region to caching-inhibited
353 * so that flash can be erased properly.
356 /* Flush d-cache and invalidate i-cache of any FLASH data */
360 if (flash_esel == -1) {
361 /* very unlikely unless something is messed up */
362 puts("Error: Could not find TLB for FLASH BASE\n");
363 flash_esel = 2; /* give our best effort to continue */
365 /* invalidate existing TLB entry for flash + promjet */
366 disable_tlb(flash_esel);
369 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
370 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
371 0, flash_esel, BOOKE_PAGESZ_256M, 1);
373 /* Disable remote I2C connection to qixis fpga */
374 QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
377 * Adjust core voltage according to voltage ID
378 * This function changes I2C mux to channel 2.
381 printf("Warning: Adjusting core voltage failed.\n");
383 brd_mux_lane_to_slot();
384 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
389 unsigned long get_board_sys_clk(void)
391 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
392 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
393 /* use accurate clock measurement */
394 int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
395 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
400 debug("SYS Clock measurement is: %d\n", val);
403 printf("Warning: SYS clock measurement is invalid, ");
404 printf("using value from brdcfg1.\n");
408 switch (sysclk_conf & 0x0F) {
409 case QIXIS_SYSCLK_83:
411 case QIXIS_SYSCLK_100:
413 case QIXIS_SYSCLK_125:
415 case QIXIS_SYSCLK_133:
417 case QIXIS_SYSCLK_150:
419 case QIXIS_SYSCLK_160:
421 case QIXIS_SYSCLK_166:
427 unsigned long get_board_ddr_clk(void)
429 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
430 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
431 /* use accurate clock measurement */
432 int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
433 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
438 debug("DDR Clock measurement is: %d\n", val);
441 printf("Warning: DDR clock measurement is invalid, ");
442 printf("using value from brdcfg1.\n");
446 switch ((ddrclk_conf & 0x30) >> 4) {
447 case QIXIS_DDRCLK_100:
449 case QIXIS_DDRCLK_125:
451 case QIXIS_DDRCLK_133:
457 int misc_init_r(void)
462 int ft_board_setup(void *blob, bd_t *bd)
467 ft_cpu_setup(blob, bd);
469 base = env_get_bootm_low();
470 size = env_get_bootm_size();
472 fdt_fixup_memory(blob, (u64)base, (u64)size);
475 pci_of_setup(blob, bd);
478 fdt_fixup_liodn(blob);
479 fsl_fdt_fixup_dr_usb(blob, bd);
481 #ifdef CONFIG_SYS_DPAA_FMAN
482 fdt_fixup_fman_ethernet(blob);
483 fdt_fixup_board_enet(blob);