board/freescale/t208xqds/t208xqds.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2009-2013 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <env.h>
  10 #include <fdt_support.h>
  11 #include <i2c.h>
  12 #include <image.h>
  13 #include <init.h>
  14 #include <log.h>
  15 #include <netdev.h>
  16 #include <asm/global_data.h>
  17 #include <linux/compiler.h>
  18 #include <asm/mmu.h>
  19 #include <asm/processor.h>
  20 #include <asm/immap_85xx.h>
  21 #include <asm/fsl_law.h>
  22 #include <asm/fsl_serdes.h>
  23 #include <asm/fsl_liodn.h>
  24 #include <fm_eth.h>
  25 #include "../common/i2c_mux.h"
  26
  27 #include "../common/qixis.h"
  28 #include "../common/vsc3316_3308.h"
  29 #include "../common/vid.h"
  30 #include "t208xqds.h"
  31 #include "t208xqds_qixis.h"
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 int checkboard(void)
  36 {
  37         char buf[64];
  38         u8 sw;
  39         struct cpu_type *cpu = gd->arch.cpu;
  40         static const char *freq[4] = {
  41                 "100.00MHZ(from 8T49N222A)", "125.00MHz",
  42                 "156.25MHZ", "100.00MHz"
  43         };
  44
  45         printf("Board: %sQDS, ", cpu->name);
  46         sw = QIXIS_READ(arch);
  47         printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
  48         printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
  49
  50 #ifdef CONFIG_SDCARD
  51         puts("SD/MMC\n");
  52 #elif CONFIG_SPIFLASH
  53         puts("SPI\n");
  54 #else
  55         sw = QIXIS_READ(brdcfg[0]);
  56         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  57
  58         if (sw < 0x8)
  59                 printf("vBank%d\n", sw);
  60         else if (sw == 0x8)
  61                 puts("Promjet\n");
  62         else if (sw == 0x9)
  63                 puts("NAND\n");
  64         else
  65                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  66 #endif
  67
  68         printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver),
  69                qixis_read_tag(buf), (int)qixis_read_minor());
  70         /* the timestamp string contains "\n" at the end */
  71         printf(" on %s", qixis_read_time(buf));
  72
  73         puts("SERDES Reference Clocks:\n");
  74         sw = QIXIS_READ(brdcfg[2]);
  75         printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6],
  76                freq[(sw >> 4) & 0x3]);
  77         printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2],
  78                freq[sw & 0x3]);
  79
  80         return 0;
  81 }
  82
  83 int i2c_multiplexer_select_vid_channel(u8 channel)
  84 {
  85         return select_i2c_ch_pca9547(channel, 0);
  86 }
  87
  88 int brd_mux_lane_to_slot(void)
  89 {
  90         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  91         u32 srds_prtcl_s1;
  92
  93         srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
  94                                 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  95         srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  96 #if defined(CONFIG_TARGET_T2080QDS)
  97         u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
  98                                 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
  99         srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 100 #endif
 101
 102         switch (srds_prtcl_s1) {
 103         case 0:
 104                 /* SerDes1 is not enabled */
 105                 break;
 106 #if defined(CONFIG_TARGET_T2080QDS)
 107         case 0x1b:
 108         case 0x1c:
 109         case 0xa2:
 110                 /* SD1(A:D) => SLOT3 SGMII
 111                  * SD1(G:H) => SLOT1 SGMII
 112                  */
 113                 QIXIS_WRITE(brdcfg[12], 0x1a);
 114                 break;
 115         case 0x94:
 116         case 0x95:
 117                 /* SD1(A:B) => SLOT3 SGMII@1.25bps
 118                  * SD1(C:D) => SFP Module, SGMII@3.125bps
 119                  * SD1(E:H) => SLOT1 SGMII@1.25bps
 120                  */
 121         case 0x96:
 122                 /* SD1(A:B) => SLOT3 SGMII@1.25bps
 123                  * SD1(C)   => SFP Module, SGMII@3.125bps
 124                  * SD1(D)   => SFP Module, SGMII@1.25bps
 125                  * SD1(E:H) => SLOT1 PCIe4 x4
 126                  */
 127                 QIXIS_WRITE(brdcfg[12], 0x3a);
 128                 break;
 129         case 0x50:
 130         case 0x51:
 131                 /* SD1(A:D) => SLOT3 XAUI
 132                  * SD1(E)   => SLOT1 PCIe4
 133                  * SD1(F:H) => SLOT2 SGMII
 134                  */
 135                 QIXIS_WRITE(brdcfg[12], 0x15);
 136                 break;
 137         case 0x66:
 138         case 0x67:
 139                 /* SD1(A:D) => XFI cage
 140                  * SD1(E:H) => SLOT1 PCIe4
 141                  */
 142                 QIXIS_WRITE(brdcfg[12], 0xfe);
 143                 break;
 144         case 0x6a:
 145         case 0x6b:
 146                 /* SD1(A:D) => XFI cage
 147                  * SD1(E)   => SLOT1 PCIe4
 148                  * SD1(F:H) => SLOT2 SGMII
 149                  */
 150                 QIXIS_WRITE(brdcfg[12], 0xf1);
 151                 break;
 152         case 0x6c:
 153         case 0x6d:
 154                 /* SD1(A:B) => XFI cage
 155                  * SD1(C:D) => SLOT3 SGMII
 156                  * SD1(E:H) => SLOT1 PCIe4
 157                  */
 158                 QIXIS_WRITE(brdcfg[12], 0xda);
 159                 break;
 160         case 0x6e:
 161                 /* SD1(A:B) => SFP Module, XFI
 162                  * SD1(C:D) => SLOT3 SGMII
 163                  * SD1(E:F) => SLOT1 PCIe4 x2
 164                  * SD1(G:H) => SLOT2 SGMII
 165                  */
 166                 QIXIS_WRITE(brdcfg[12], 0xd9);
 167                 break;
 168         case 0xda:
 169                 /* SD1(A:H) => SLOT3 PCIe3 x8
 170                  */
 171                  QIXIS_WRITE(brdcfg[12], 0x0);
 172                  break;
 173         case 0xc8:
 174                 /* SD1(A)   => SLOT3 PCIe3 x1
 175                  * SD1(B)   => SFP Module, SGMII@1.25bps
 176                  * SD1(C:D) => SFP Module, SGMII@3.125bps
 177                  * SD1(E:F) => SLOT1 PCIe4 x2
 178                  * SD1(G:H) => SLOT2 SGMII
 179                  */
 180                  QIXIS_WRITE(brdcfg[12], 0x79);
 181                  break;
 182         case 0xab:
 183                 /* SD1(A:D) => SLOT3 PCIe3 x4
 184                  * SD1(E:H) => SLOT1 PCIe4 x4
 185                  */
 186                  QIXIS_WRITE(brdcfg[12], 0x1a);
 187                  break;
 188 #endif
 189         default:
 190                 printf("WARNING: unsupported for SerDes1 Protocol %d\n",
 191                        srds_prtcl_s1);
 192                 return -1;
 193         }
 194
 195 #ifdef CONFIG_TARGET_T2080QDS
 196         switch (srds_prtcl_s2) {
 197         case 0:
 198                 /* SerDes2 is not enabled */
 199                 break;
 200         case 0x01:
 201         case 0x02:
 202                 /* SD2(A:H) => SLOT4 PCIe1 */
 203                 QIXIS_WRITE(brdcfg[13], 0x10);
 204                 break;
 205         case 0x15:
 206         case 0x16:
 207                 /*
 208                  * SD2(A:D) => SLOT4 PCIe1
 209                  * SD2(E:F) => SLOT5 PCIe2
 210                  * SD2(G:H) => SATA1,SATA2
 211                  */
 212                 QIXIS_WRITE(brdcfg[13], 0xb0);
 213                 break;
 214         case 0x18:
 215                 /*
 216                  * SD2(A:D) => SLOT4 PCIe1
 217                  * SD2(E:F) => SLOT5 Aurora
 218                  * SD2(G:H) => SATA1,SATA2
 219                  */
 220                 QIXIS_WRITE(brdcfg[13], 0x78);
 221                 break;
 222         case 0x1f:
 223                 /*
 224                  * SD2(A:D) => SLOT4 PCIe1
 225                  * SD2(E:H) => SLOT5 PCIe2
 226                  */
 227                 QIXIS_WRITE(brdcfg[13], 0xa0);
 228                 break;
 229         case 0x29:
 230         case 0x2d:
 231         case 0x2e:
 232                 /*
 233                  * SD2(A:D) => SLOT4 SRIO2
 234                  * SD2(E:H) => SLOT5 SRIO1
 235                  */
 236                 QIXIS_WRITE(brdcfg[13], 0xa0);
 237                 break;
 238         case 0x36:
 239                 /*
 240                  * SD2(A:D) => SLOT4 SRIO2
 241                  * SD2(E:F) => Aurora
 242                  * SD2(G:H) => SATA1,SATA2
 243                  */
 244                 QIXIS_WRITE(brdcfg[13], 0x78);
 245                 break;
 246         default:
 247                 printf("WARNING: unsupported for SerDes2 Protocol %d\n",
 248                        srds_prtcl_s2);
 249                 return -1;
 250         }
 251 #endif
 252         return 0;
 253 }
 254
 255 static void esdhc_adapter_card_ident(void)
 256 {
 257         u8 card_id, value;
 258
 259         card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
 260
 261         switch (card_id) {
 262         case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
 263                 value = QIXIS_READ(brdcfg[5]);
 264                 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
 265                 QIXIS_WRITE(brdcfg[5], value);
 266                 break;
 267         case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
 268                 value = QIXIS_READ(pwr_ctl[1]);
 269                 value |= QIXIS_EVDD_BY_SDHC_VS;
 270                 QIXIS_WRITE(pwr_ctl[1], value);
 271                 break;
 272         case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
 273                 value = QIXIS_READ(brdcfg[5]);
 274                 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
 275                 QIXIS_WRITE(brdcfg[5], value);
 276                 break;
 277         default:
 278                 break;
 279         }
 280 }
 281
 282 int board_early_init_r(void)
 283 {
 284         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 285         int flash_esel = find_tlb_idx((void *)flashbase, 1);
 286
 287         /*
 288          * Remap Boot flash + PROMJET region to caching-inhibited
 289          * so that flash can be erased properly.
 290          */
 291
 292         /* Flush d-cache and invalidate i-cache of any FLASH data */
 293         flush_dcache();
 294         invalidate_icache();
 295
 296         if (flash_esel == -1) {
 297                 /* very unlikely unless something is messed up */
 298                 puts("Error: Could not find TLB for FLASH BASE\n");
 299                 flash_esel = 2; /* give our best effort to continue */
 300         } else {
 301                 /* invalidate existing TLB entry for flash + promjet */
 302                 disable_tlb(flash_esel);
 303         }
 304
 305         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 306                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 307                 0, flash_esel, BOOKE_PAGESZ_256M, 1);
 308
 309         /* Disable remote I2C connection to qixis fpga */
 310         QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
 311
 312         /*
 313          * Adjust core voltage according to voltage ID
 314          * This function changes I2C mux to channel 2.
 315          */
 316         if (adjust_vdd(0))
 317                 printf("Warning: Adjusting core voltage failed.\n");
 318
 319         brd_mux_lane_to_slot();
 320         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 321         esdhc_adapter_card_ident();
 322         return 0;
 323 }
 324
 325 unsigned long get_board_sys_clk(void)
 326 {
 327         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 328 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
 329         /* use accurate clock measurement */
 330         int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
 331         int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
 332         u32 val;
 333
 334         val =  freq * base;
 335         if (val) {
 336                 debug("SYS Clock measurement is: %d\n", val);
 337                 return val;
 338         } else {
 339                 printf("Warning: SYS clock measurement is invalid, ");
 340                 printf("using value from brdcfg1.\n");
 341         }
 342 #endif
 343
 344         switch (sysclk_conf & 0x0F) {
 345         case QIXIS_SYSCLK_83:
 346                 return 83333333;
 347         case QIXIS_SYSCLK_100:
 348                 return 100000000;
 349         case QIXIS_SYSCLK_125:
 350                 return 125000000;
 351         case QIXIS_SYSCLK_133:
 352                 return 133333333;
 353         case QIXIS_SYSCLK_150:
 354                 return 150000000;
 355         case QIXIS_SYSCLK_160:
 356                 return 160000000;
 357         case QIXIS_SYSCLK_166:
 358                 return 166666666;
 359         }
 360         return 66666666;
 361 }
 362
 363 unsigned long get_board_ddr_clk(void)
 364 {
 365         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 366 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
 367         /* use accurate clock measurement */
 368         int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
 369         int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
 370         u32 val;
 371
 372         val =  freq * base;
 373         if (val) {
 374                 debug("DDR Clock measurement is: %d\n", val);
 375                 return val;
 376         } else {
 377                 printf("Warning: DDR clock measurement is invalid, ");
 378                 printf("using value from brdcfg1.\n");
 379         }
 380 #endif
 381
 382         switch ((ddrclk_conf & 0x30) >> 4) {
 383         case QIXIS_DDRCLK_100:
 384                 return 100000000;
 385         case QIXIS_DDRCLK_125:
 386                 return 125000000;
 387         case QIXIS_DDRCLK_133:
 388                 return 133333333;
 389         }
 390         return 66666666;
 391 }
 392
 393 int misc_init_r(void)
 394 {
 395         return 0;
 396 }
 397
 398 int ft_board_setup(void *blob, struct bd_info *bd)
 399 {
 400         phys_addr_t base;
 401         phys_size_t size;
 402
 403         ft_cpu_setup(blob, bd);
 404
 405         base = env_get_bootm_low();
 406         size = env_get_bootm_size();
 407
 408         fdt_fixup_memory(blob, (u64)base, (u64)size);
 409
 410 #ifdef CONFIG_PCI
 411         pci_of_setup(blob, bd);
 412 #endif
 413
 414         fdt_fixup_liodn(blob);
 415         fsl_fdt_fixup_dr_usb(blob, bd);
 416
 417 #ifdef CONFIG_SYS_DPAA_FMAN
 418 #ifndef CONFIG_DM_ETH
 419         fdt_fixup_fman_ethernet(blob);
 420 #endif
 421         fdt_fixup_board_enet(blob);
 422 #endif
 423
 424         return 0;
 425 }