1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2013 Freescale Semiconductor, Inc.
10 #include <fdt_support.h>
16 #include <asm/global_data.h>
17 #include <linux/compiler.h>
19 #include <asm/processor.h>
20 #include <asm/immap_85xx.h>
21 #include <asm/fsl_law.h>
22 #include <asm/fsl_serdes.h>
23 #include <asm/fsl_liodn.h>
25 #include "../common/i2c_mux.h"
27 #include "../common/qixis.h"
28 #include "../common/vsc3316_3308.h"
29 #include "../common/vid.h"
31 #include "t208xqds_qixis.h"
33 DECLARE_GLOBAL_DATA_PTR;
39 struct cpu_type *cpu = gd->arch.cpu;
40 static const char *freq[4] = {
41 "100.00MHZ(from 8T49N222A)", "125.00MHz",
42 "156.25MHZ", "100.00MHz"
45 printf("Board: %sQDS, ", cpu->name);
46 sw = QIXIS_READ(arch);
47 printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
48 printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
55 sw = QIXIS_READ(brdcfg[0]);
56 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
59 printf("vBank%d\n", sw);
65 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
68 printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver),
69 qixis_read_tag(buf), (int)qixis_read_minor());
70 /* the timestamp string contains "\n" at the end */
71 printf(" on %s", qixis_read_time(buf));
73 puts("SERDES Reference Clocks:\n");
74 sw = QIXIS_READ(brdcfg[2]);
75 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6],
76 freq[(sw >> 4) & 0x3]);
77 printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2],
83 int i2c_multiplexer_select_vid_channel(u8 channel)
85 return select_i2c_ch_pca9547(channel, 0);
88 int brd_mux_lane_to_slot(void)
90 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
93 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
94 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
95 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
96 #if defined(CONFIG_TARGET_T2080QDS)
97 u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
98 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
99 srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
102 switch (srds_prtcl_s1) {
104 /* SerDes1 is not enabled */
106 #if defined(CONFIG_TARGET_T2080QDS)
110 /* SD1(A:D) => SLOT3 SGMII
111 * SD1(G:H) => SLOT1 SGMII
113 QIXIS_WRITE(brdcfg[12], 0x1a);
117 /* SD1(A:B) => SLOT3 SGMII@1.25bps
118 * SD1(C:D) => SFP Module, SGMII@3.125bps
119 * SD1(E:H) => SLOT1 SGMII@1.25bps
122 /* SD1(A:B) => SLOT3 SGMII@1.25bps
123 * SD1(C) => SFP Module, SGMII@3.125bps
124 * SD1(D) => SFP Module, SGMII@1.25bps
125 * SD1(E:H) => SLOT1 PCIe4 x4
127 QIXIS_WRITE(brdcfg[12], 0x3a);
131 /* SD1(A:D) => SLOT3 XAUI
132 * SD1(E) => SLOT1 PCIe4
133 * SD1(F:H) => SLOT2 SGMII
135 QIXIS_WRITE(brdcfg[12], 0x15);
139 /* SD1(A:D) => XFI cage
140 * SD1(E:H) => SLOT1 PCIe4
142 QIXIS_WRITE(brdcfg[12], 0xfe);
146 /* SD1(A:D) => XFI cage
147 * SD1(E) => SLOT1 PCIe4
148 * SD1(F:H) => SLOT2 SGMII
150 QIXIS_WRITE(brdcfg[12], 0xf1);
154 /* SD1(A:B) => XFI cage
155 * SD1(C:D) => SLOT3 SGMII
156 * SD1(E:H) => SLOT1 PCIe4
158 QIXIS_WRITE(brdcfg[12], 0xda);
161 /* SD1(A:B) => SFP Module, XFI
162 * SD1(C:D) => SLOT3 SGMII
163 * SD1(E:F) => SLOT1 PCIe4 x2
164 * SD1(G:H) => SLOT2 SGMII
166 QIXIS_WRITE(brdcfg[12], 0xd9);
169 /* SD1(A:H) => SLOT3 PCIe3 x8
171 QIXIS_WRITE(brdcfg[12], 0x0);
174 /* SD1(A) => SLOT3 PCIe3 x1
175 * SD1(B) => SFP Module, SGMII@1.25bps
176 * SD1(C:D) => SFP Module, SGMII@3.125bps
177 * SD1(E:F) => SLOT1 PCIe4 x2
178 * SD1(G:H) => SLOT2 SGMII
180 QIXIS_WRITE(brdcfg[12], 0x79);
183 /* SD1(A:D) => SLOT3 PCIe3 x4
184 * SD1(E:H) => SLOT1 PCIe4 x4
186 QIXIS_WRITE(brdcfg[12], 0x1a);
190 printf("WARNING: unsupported for SerDes1 Protocol %d\n",
195 #ifdef CONFIG_TARGET_T2080QDS
196 switch (srds_prtcl_s2) {
198 /* SerDes2 is not enabled */
202 /* SD2(A:H) => SLOT4 PCIe1 */
203 QIXIS_WRITE(brdcfg[13], 0x10);
208 * SD2(A:D) => SLOT4 PCIe1
209 * SD2(E:F) => SLOT5 PCIe2
210 * SD2(G:H) => SATA1,SATA2
212 QIXIS_WRITE(brdcfg[13], 0xb0);
216 * SD2(A:D) => SLOT4 PCIe1
217 * SD2(E:F) => SLOT5 Aurora
218 * SD2(G:H) => SATA1,SATA2
220 QIXIS_WRITE(brdcfg[13], 0x78);
224 * SD2(A:D) => SLOT4 PCIe1
225 * SD2(E:H) => SLOT5 PCIe2
227 QIXIS_WRITE(brdcfg[13], 0xa0);
233 * SD2(A:D) => SLOT4 SRIO2
234 * SD2(E:H) => SLOT5 SRIO1
236 QIXIS_WRITE(brdcfg[13], 0xa0);
240 * SD2(A:D) => SLOT4 SRIO2
242 * SD2(G:H) => SATA1,SATA2
244 QIXIS_WRITE(brdcfg[13], 0x78);
247 printf("WARNING: unsupported for SerDes2 Protocol %d\n",
255 static void esdhc_adapter_card_ident(void)
259 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
262 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
263 value = QIXIS_READ(brdcfg[5]);
264 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
265 QIXIS_WRITE(brdcfg[5], value);
267 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
268 value = QIXIS_READ(pwr_ctl[1]);
269 value |= QIXIS_EVDD_BY_SDHC_VS;
270 QIXIS_WRITE(pwr_ctl[1], value);
272 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
273 value = QIXIS_READ(brdcfg[5]);
274 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
275 QIXIS_WRITE(brdcfg[5], value);
282 int board_early_init_r(void)
284 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
285 int flash_esel = find_tlb_idx((void *)flashbase, 1);
288 * Remap Boot flash + PROMJET region to caching-inhibited
289 * so that flash can be erased properly.
292 /* Flush d-cache and invalidate i-cache of any FLASH data */
296 if (flash_esel == -1) {
297 /* very unlikely unless something is messed up */
298 puts("Error: Could not find TLB for FLASH BASE\n");
299 flash_esel = 2; /* give our best effort to continue */
301 /* invalidate existing TLB entry for flash + promjet */
302 disable_tlb(flash_esel);
305 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
306 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
307 0, flash_esel, BOOKE_PAGESZ_256M, 1);
309 /* Disable remote I2C connection to qixis fpga */
310 QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
313 * Adjust core voltage according to voltage ID
314 * This function changes I2C mux to channel 2.
317 printf("Warning: Adjusting core voltage failed.\n");
319 brd_mux_lane_to_slot();
320 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
321 esdhc_adapter_card_ident();
325 unsigned long get_board_sys_clk(void)
327 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
328 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
329 /* use accurate clock measurement */
330 int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
331 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
336 debug("SYS Clock measurement is: %d\n", val);
339 printf("Warning: SYS clock measurement is invalid, ");
340 printf("using value from brdcfg1.\n");
344 switch (sysclk_conf & 0x0F) {
345 case QIXIS_SYSCLK_83:
347 case QIXIS_SYSCLK_100:
349 case QIXIS_SYSCLK_125:
351 case QIXIS_SYSCLK_133:
353 case QIXIS_SYSCLK_150:
355 case QIXIS_SYSCLK_160:
357 case QIXIS_SYSCLK_166:
363 unsigned long get_board_ddr_clk(void)
365 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
366 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
367 /* use accurate clock measurement */
368 int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
369 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
374 debug("DDR Clock measurement is: %d\n", val);
377 printf("Warning: DDR clock measurement is invalid, ");
378 printf("using value from brdcfg1.\n");
382 switch ((ddrclk_conf & 0x30) >> 4) {
383 case QIXIS_DDRCLK_100:
385 case QIXIS_DDRCLK_125:
387 case QIXIS_DDRCLK_133:
393 int misc_init_r(void)
398 int ft_board_setup(void *blob, struct bd_info *bd)
403 ft_cpu_setup(blob, bd);
405 base = env_get_bootm_low();
406 size = env_get_bootm_size();
408 fdt_fixup_memory(blob, (u64)base, (u64)size);
411 pci_of_setup(blob, bd);
414 fdt_fixup_liodn(blob);
415 fsl_fdt_fixup_dr_usb(blob, bd);
417 #ifdef CONFIG_SYS_DPAA_FMAN
418 #ifndef CONFIG_DM_ETH
419 fdt_fixup_fman_ethernet(blob);
421 fdt_fixup_board_enet(blob);