1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2013 Freescale Semiconductor, Inc.
10 #include <fdt_support.h>
16 #include <asm/global_data.h>
17 #include <linux/compiler.h>
19 #include <asm/processor.h>
20 #include <asm/immap_85xx.h>
21 #include <asm/fsl_law.h>
22 #include <asm/fsl_serdes.h>
23 #include <asm/fsl_liodn.h>
26 #include "../common/qixis.h"
27 #include "../common/vsc3316_3308.h"
28 #include "../common/vid.h"
30 #include "t208xqds_qixis.h"
32 DECLARE_GLOBAL_DATA_PTR;
38 struct cpu_type *cpu = gd->arch.cpu;
39 static const char *freq[4] = {
40 "100.00MHZ(from 8T49N222A)", "125.00MHz",
41 "156.25MHZ", "100.00MHz"
44 printf("Board: %sQDS, ", cpu->name);
45 sw = QIXIS_READ(arch);
46 printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
47 printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
54 sw = QIXIS_READ(brdcfg[0]);
55 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
58 printf("vBank%d\n", sw);
64 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
67 printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver),
68 qixis_read_tag(buf), (int)qixis_read_minor());
69 /* the timestamp string contains "\n" at the end */
70 printf(" on %s", qixis_read_time(buf));
72 puts("SERDES Reference Clocks:\n");
73 sw = QIXIS_READ(brdcfg[2]);
74 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6],
75 freq[(sw >> 4) & 0x3]);
76 printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2],
82 int select_i2c_ch_pca9547(u8 ch, int bus_num)
86 #if CONFIG_IS_ENABLED(DM_I2C)
89 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
91 printf("%s: Cannot find udev for a bus %d\n", __func__,
95 ret = dm_i2c_write(dev, 0, &ch, 1);
97 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
100 puts("PCA: failed to select proper channel\n");
107 int i2c_multiplexer_select_vid_channel(u8 channel)
109 return select_i2c_ch_pca9547(channel, 0);
112 int brd_mux_lane_to_slot(void)
114 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
117 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
118 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
119 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
120 #if defined(CONFIG_TARGET_T2080QDS)
121 u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
122 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
123 srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
126 switch (srds_prtcl_s1) {
128 /* SerDes1 is not enabled */
130 #if defined(CONFIG_TARGET_T2080QDS)
134 /* SD1(A:D) => SLOT3 SGMII
135 * SD1(G:H) => SLOT1 SGMII
137 QIXIS_WRITE(brdcfg[12], 0x1a);
141 /* SD1(A:B) => SLOT3 SGMII@1.25bps
142 * SD1(C:D) => SFP Module, SGMII@3.125bps
143 * SD1(E:H) => SLOT1 SGMII@1.25bps
146 /* SD1(A:B) => SLOT3 SGMII@1.25bps
147 * SD1(C) => SFP Module, SGMII@3.125bps
148 * SD1(D) => SFP Module, SGMII@1.25bps
149 * SD1(E:H) => SLOT1 PCIe4 x4
151 QIXIS_WRITE(brdcfg[12], 0x3a);
155 /* SD1(A:D) => SLOT3 XAUI
156 * SD1(E) => SLOT1 PCIe4
157 * SD1(F:H) => SLOT2 SGMII
159 QIXIS_WRITE(brdcfg[12], 0x15);
163 /* SD1(A:D) => XFI cage
164 * SD1(E:H) => SLOT1 PCIe4
166 QIXIS_WRITE(brdcfg[12], 0xfe);
170 /* SD1(A:D) => XFI cage
171 * SD1(E) => SLOT1 PCIe4
172 * SD1(F:H) => SLOT2 SGMII
174 QIXIS_WRITE(brdcfg[12], 0xf1);
178 /* SD1(A:B) => XFI cage
179 * SD1(C:D) => SLOT3 SGMII
180 * SD1(E:H) => SLOT1 PCIe4
182 QIXIS_WRITE(brdcfg[12], 0xda);
185 /* SD1(A:B) => SFP Module, XFI
186 * SD1(C:D) => SLOT3 SGMII
187 * SD1(E:F) => SLOT1 PCIe4 x2
188 * SD1(G:H) => SLOT2 SGMII
190 QIXIS_WRITE(brdcfg[12], 0xd9);
193 /* SD1(A:H) => SLOT3 PCIe3 x8
195 QIXIS_WRITE(brdcfg[12], 0x0);
198 /* SD1(A) => SLOT3 PCIe3 x1
199 * SD1(B) => SFP Module, SGMII@1.25bps
200 * SD1(C:D) => SFP Module, SGMII@3.125bps
201 * SD1(E:F) => SLOT1 PCIe4 x2
202 * SD1(G:H) => SLOT2 SGMII
204 QIXIS_WRITE(brdcfg[12], 0x79);
207 /* SD1(A:D) => SLOT3 PCIe3 x4
208 * SD1(E:H) => SLOT1 PCIe4 x4
210 QIXIS_WRITE(brdcfg[12], 0x1a);
212 #elif defined(CONFIG_TARGET_T2081QDS)
215 /* SD1(A:D) => SLOT2 XAUI
216 * SD1(E) => SLOT1 PCIe4 x1
217 * SD1(F:H) => SLOT3 SGMII
219 QIXIS_WRITE(brdcfg[12], 0x98);
220 QIXIS_WRITE(brdcfg[13], 0x70);
224 /* SD1(A:D) => XFI SFP Module
225 * SD1(E) => SLOT1 PCIe4 x1
226 * SD1(F:H) => SLOT3 SGMII
228 QIXIS_WRITE(brdcfg[12], 0x80);
229 QIXIS_WRITE(brdcfg[13], 0x70);
233 /* SD1(A:B) => XFI SFP Module
234 * SD1(C:D) => SLOT2 SGMII
235 * SD1(E:H) => SLOT1 PCIe4 x4
237 QIXIS_WRITE(brdcfg[12], 0xe8);
238 QIXIS_WRITE(brdcfg[13], 0x0);
242 /* SD1(A:D) => SLOT2 PCIe3 x4
243 * SD1(F:H) => SLOT1 SGMI4 x4
245 QIXIS_WRITE(brdcfg[12], 0xf8);
246 QIXIS_WRITE(brdcfg[13], 0x0);
250 /* SD1(A) => SLOT2 PCIe3 x1
251 * SD1(B) => SLOT7 SGMII
252 * SD1(C) => SLOT6 SGMII
253 * SD1(D) => SLOT5 SGMII
254 * SD1(E) => SLOT1 PCIe4 x1
255 * SD1(F:H) => SLOT3 SGMII
257 QIXIS_WRITE(brdcfg[12], 0x80);
258 QIXIS_WRITE(brdcfg[13], 0x70);
262 /* SD1(A:D) => SLOT2 PCIe3 x4
263 * SD1(E) => SLOT1 PCIe4 x1
264 * SD1(F) => SLOT4 PCIe1 x1
265 * SD1(G) => SLOT3 PCIe2 x1
266 * SD1(H) => SLOT7 SGMII
268 QIXIS_WRITE(brdcfg[12], 0x98);
269 QIXIS_WRITE(brdcfg[13], 0x25);
272 /* SD1(A) => SLOT2 PCIe3 x1
273 * SD1(B:D) => SLOT7 SGMII
274 * SD1(E) => SLOT1 PCIe4 x1
275 * SD1(F) => SLOT4 PCIe1 x1
276 * SD1(G) => SLOT3 PCIe2 x1
277 * SD1(H) => SLOT7 SGMII
279 QIXIS_WRITE(brdcfg[12], 0x81);
280 QIXIS_WRITE(brdcfg[13], 0xa5);
284 printf("WARNING: unsupported for SerDes1 Protocol %d\n",
289 #ifdef CONFIG_TARGET_T2080QDS
290 switch (srds_prtcl_s2) {
292 /* SerDes2 is not enabled */
296 /* SD2(A:H) => SLOT4 PCIe1 */
297 QIXIS_WRITE(brdcfg[13], 0x10);
302 * SD2(A:D) => SLOT4 PCIe1
303 * SD2(E:F) => SLOT5 PCIe2
304 * SD2(G:H) => SATA1,SATA2
306 QIXIS_WRITE(brdcfg[13], 0xb0);
310 * SD2(A:D) => SLOT4 PCIe1
311 * SD2(E:F) => SLOT5 Aurora
312 * SD2(G:H) => SATA1,SATA2
314 QIXIS_WRITE(brdcfg[13], 0x78);
318 * SD2(A:D) => SLOT4 PCIe1
319 * SD2(E:H) => SLOT5 PCIe2
321 QIXIS_WRITE(brdcfg[13], 0xa0);
327 * SD2(A:D) => SLOT4 SRIO2
328 * SD2(E:H) => SLOT5 SRIO1
330 QIXIS_WRITE(brdcfg[13], 0xa0);
334 * SD2(A:D) => SLOT4 SRIO2
336 * SD2(G:H) => SATA1,SATA2
338 QIXIS_WRITE(brdcfg[13], 0x78);
341 printf("WARNING: unsupported for SerDes2 Protocol %d\n",
349 static void esdhc_adapter_card_ident(void)
353 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
356 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
357 value = QIXIS_READ(brdcfg[5]);
358 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
359 QIXIS_WRITE(brdcfg[5], value);
361 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
362 value = QIXIS_READ(pwr_ctl[1]);
363 value |= QIXIS_EVDD_BY_SDHC_VS;
364 QIXIS_WRITE(pwr_ctl[1], value);
366 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
367 value = QIXIS_READ(brdcfg[5]);
368 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
369 QIXIS_WRITE(brdcfg[5], value);
376 int board_early_init_r(void)
378 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
379 int flash_esel = find_tlb_idx((void *)flashbase, 1);
382 * Remap Boot flash + PROMJET region to caching-inhibited
383 * so that flash can be erased properly.
386 /* Flush d-cache and invalidate i-cache of any FLASH data */
390 if (flash_esel == -1) {
391 /* very unlikely unless something is messed up */
392 puts("Error: Could not find TLB for FLASH BASE\n");
393 flash_esel = 2; /* give our best effort to continue */
395 /* invalidate existing TLB entry for flash + promjet */
396 disable_tlb(flash_esel);
399 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
400 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
401 0, flash_esel, BOOKE_PAGESZ_256M, 1);
403 /* Disable remote I2C connection to qixis fpga */
404 QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
407 * Adjust core voltage according to voltage ID
408 * This function changes I2C mux to channel 2.
411 printf("Warning: Adjusting core voltage failed.\n");
413 brd_mux_lane_to_slot();
414 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
415 esdhc_adapter_card_ident();
419 unsigned long get_board_sys_clk(void)
421 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
422 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
423 /* use accurate clock measurement */
424 int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
425 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
430 debug("SYS Clock measurement is: %d\n", val);
433 printf("Warning: SYS clock measurement is invalid, ");
434 printf("using value from brdcfg1.\n");
438 switch (sysclk_conf & 0x0F) {
439 case QIXIS_SYSCLK_83:
441 case QIXIS_SYSCLK_100:
443 case QIXIS_SYSCLK_125:
445 case QIXIS_SYSCLK_133:
447 case QIXIS_SYSCLK_150:
449 case QIXIS_SYSCLK_160:
451 case QIXIS_SYSCLK_166:
457 unsigned long get_board_ddr_clk(void)
459 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
460 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
461 /* use accurate clock measurement */
462 int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
463 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
468 debug("DDR Clock measurement is: %d\n", val);
471 printf("Warning: DDR clock measurement is invalid, ");
472 printf("using value from brdcfg1.\n");
476 switch ((ddrclk_conf & 0x30) >> 4) {
477 case QIXIS_DDRCLK_100:
479 case QIXIS_DDRCLK_125:
481 case QIXIS_DDRCLK_133:
487 int misc_init_r(void)
492 int ft_board_setup(void *blob, struct bd_info *bd)
497 ft_cpu_setup(blob, bd);
499 base = env_get_bootm_low();
500 size = env_get_bootm_size();
502 fdt_fixup_memory(blob, (u64)base, (u64)size);
505 pci_of_setup(blob, bd);
508 fdt_fixup_liodn(blob);
509 fsl_fdt_fixup_dr_usb(blob, bd);
511 #ifdef CONFIG_SYS_DPAA_FMAN
512 #ifndef CONFIG_DM_ETH
513 fdt_fixup_fman_ethernet(blob);
515 fdt_fixup_board_enet(blob);