1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2013 Freescale Semiconductor, Inc.
6 * Shengzhou Liu <Shengzhou.Liu@freescale.com>
11 #include <fdt_support.h>
16 #include <asm/processor.h>
17 #include <asm/immap_85xx.h>
18 #include <asm/fsl_law.h>
19 #include <asm/fsl_serdes.h>
20 #include <asm/fsl_portals.h>
21 #include <asm/fsl_liodn.h>
27 #include <fsl_dtsec.h>
28 #include <asm/fsl_serdes.h>
30 #include "../common/qixis.h"
31 #include "../common/fman.h"
32 #include "t208xqds_qixis.h"
33 #include <linux/libfdt.h>
35 #define EMI_NONE 0xFFFFFFFF
39 #if defined(CONFIG_TARGET_T2080QDS)
45 #elif defined(CONFIG_TARGET_T2081QDS)
54 #define PCCR1_SGMIIA_KX_MASK 0x00008000
55 #define PCCR1_SGMIIB_KX_MASK 0x00004000
56 #define PCCR1_SGMIIC_KX_MASK 0x00002000
57 #define PCCR1_SGMIID_KX_MASK 0x00001000
58 #define PCCR1_SGMIIE_KX_MASK 0x00000800
59 #define PCCR1_SGMIIF_KX_MASK 0x00000400
60 #define PCCR1_SGMIIG_KX_MASK 0x00000200
61 #define PCCR1_SGMIIH_KX_MASK 0x00000100
63 static int mdio_mux[NUM_FM_PORTS];
65 static const char * const mdio_names[] = {
66 #if defined(CONFIG_TARGET_T2080QDS)
67 "T2080QDS_MDIO_RGMII1",
68 "T2080QDS_MDIO_RGMII2",
69 "T2080QDS_MDIO_SLOT1",
70 "T2080QDS_MDIO_SLOT3",
71 "T2080QDS_MDIO_SLOT4",
72 "T2080QDS_MDIO_SLOT5",
73 "T2080QDS_MDIO_SLOT2",
75 #elif defined(CONFIG_TARGET_T2081QDS)
76 "T2081QDS_MDIO_RGMII1",
77 "T2081QDS_MDIO_RGMII2",
78 "T2081QDS_MDIO_SLOT1",
79 "T2081QDS_MDIO_SLOT2",
80 "T2081QDS_MDIO_SLOT3",
81 "T2081QDS_MDIO_SLOT5",
82 "T2081QDS_MDIO_SLOT6",
83 "T2081QDS_MDIO_SLOT7",
88 /* Map SerDes1 8 lanes to default slot, will be initialized dynamically */
89 #if defined(CONFIG_TARGET_T2080QDS)
90 static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1};
91 #elif defined(CONFIG_TARGET_T2081QDS)
92 static u8 lane_to_slot[] = {2, 2, 2, 2, 1, 1, 1, 1};
95 static const char *t208xqds_mdio_name_for_muxval(u8 muxval)
97 return mdio_names[muxval];
100 struct mii_dev *mii_dev_for_muxval(u8 muxval)
103 const char *name = t208xqds_mdio_name_for_muxval(muxval);
106 printf("No bus for muxval %x\n", muxval);
110 bus = miiphy_get_dev_by_name(name);
113 printf("No bus by name %s\n", name);
120 struct t208xqds_mdio {
122 struct mii_dev *realbus;
125 static void t208xqds_mux_mdio(u8 muxval)
129 brdcfg4 = QIXIS_READ(brdcfg[4]);
130 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
131 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
132 QIXIS_WRITE(brdcfg[4], brdcfg4);
136 static int t208xqds_mdio_read(struct mii_dev *bus, int addr, int devad,
139 struct t208xqds_mdio *priv = bus->priv;
141 t208xqds_mux_mdio(priv->muxval);
143 return priv->realbus->read(priv->realbus, addr, devad, regnum);
146 static int t208xqds_mdio_write(struct mii_dev *bus, int addr, int devad,
147 int regnum, u16 value)
149 struct t208xqds_mdio *priv = bus->priv;
151 t208xqds_mux_mdio(priv->muxval);
153 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
156 static int t208xqds_mdio_reset(struct mii_dev *bus)
158 struct t208xqds_mdio *priv = bus->priv;
160 return priv->realbus->reset(priv->realbus);
163 static int t208xqds_mdio_init(char *realbusname, u8 muxval)
165 struct t208xqds_mdio *pmdio;
166 struct mii_dev *bus = mdio_alloc();
169 printf("Failed to allocate t208xqds MDIO bus\n");
173 pmdio = malloc(sizeof(*pmdio));
175 printf("Failed to allocate t208xqds private data\n");
180 bus->read = t208xqds_mdio_read;
181 bus->write = t208xqds_mdio_write;
182 bus->reset = t208xqds_mdio_reset;
183 strcpy(bus->name, t208xqds_mdio_name_for_muxval(muxval));
185 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
187 if (!pmdio->realbus) {
188 printf("No bus with name %s\n", realbusname);
194 pmdio->muxval = muxval;
196 return mdio_register(bus);
199 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
200 enum fm_port port, int offset)
204 char lane_mode[2][20] = {"1000BASE-KX", "10GBASE-KR"};
205 char buf[32] = "serdes-1,";
206 struct fixed_link f_link;
211 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
212 #ifdef CONFIG_TARGET_T2080QDS
213 serdes_corenet_t *srds_regs =
214 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
215 u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1);
217 u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
218 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
220 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
222 if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
223 phy = fm_info_get_phy_address(port);
225 #if defined(CONFIG_TARGET_T2080QDS)
227 if (hwconfig_sub("fsl_1gkx", "fm1_1g1")) {
229 fdt_set_phy_handle(fdt, compat, addr,
231 fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio1");
232 sprintf(buf, "%s%s%s", buf, "lane-c,",
233 (char *)lane_mode[0]);
234 out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
235 PCCR1_SGMIIH_KX_MASK);
239 if (hwconfig_sub("fsl_1gkx", "fm1_1g2")) {
241 fdt_set_phy_handle(fdt, compat, addr,
243 fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio2");
244 sprintf(buf, "%s%s%s", buf, "lane-d,",
245 (char *)lane_mode[0]);
246 out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
247 PCCR1_SGMIIG_KX_MASK);
251 if (hwconfig_sub("fsl_1gkx", "fm1_1g9")) {
253 fdt_set_phy_handle(fdt, compat, addr,
255 fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio9");
256 sprintf(buf, "%s%s%s", buf, "lane-a,",
257 (char *)lane_mode[0]);
258 out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
259 PCCR1_SGMIIE_KX_MASK);
263 if (hwconfig_sub("fsl_1gkx", "fm1_1g10")) {
265 fdt_set_phy_handle(fdt, compat, addr,
267 fdt_status_okay_by_alias(fdt,
269 sprintf(buf, "%s%s%s", buf, "lane-b,",
270 (char *)lane_mode[0]);
271 out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
272 PCCR1_SGMIIF_KX_MASK);
275 if (mdio_mux[port] == EMI1_SLOT2) {
276 sprintf(alias, "phy_sgmii_s2_%x", phy);
277 fdt_set_phy_handle(fdt, compat, addr, alias);
278 fdt_status_okay_by_alias(fdt, "emi1_slot2");
279 } else if (mdio_mux[port] == EMI1_SLOT3) {
280 sprintf(alias, "phy_sgmii_s3_%x", phy);
281 fdt_set_phy_handle(fdt, compat, addr, alias);
282 fdt_status_okay_by_alias(fdt, "emi1_slot3");
286 if (hwconfig_sub("fsl_1gkx", "fm1_1g5")) {
288 fdt_set_phy_handle(fdt, compat, addr,
290 fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio5");
291 sprintf(buf, "%s%s%s", buf, "lane-g,",
292 (char *)lane_mode[0]);
293 out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
294 PCCR1_SGMIIC_KX_MASK);
298 if (hwconfig_sub("fsl_1gkx", "fm1_1g6")) {
300 fdt_set_phy_handle(fdt, compat, addr,
302 fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio6");
303 sprintf(buf, "%s%s%s", buf, "lane-h,",
304 (char *)lane_mode[0]);
305 out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
306 PCCR1_SGMIID_KX_MASK);
309 if (mdio_mux[port] == EMI1_SLOT1) {
310 sprintf(alias, "phy_sgmii_s1_%x", phy);
311 fdt_set_phy_handle(fdt, compat, addr, alias);
312 fdt_status_okay_by_alias(fdt, "emi1_slot1");
313 } else if (mdio_mux[port] == EMI1_SLOT2) {
314 sprintf(alias, "phy_sgmii_s2_%x", phy);
315 fdt_set_phy_handle(fdt, compat, addr, alias);
316 fdt_status_okay_by_alias(fdt, "emi1_slot2");
319 #elif defined(CONFIG_TARGET_T2081QDS)
326 if (mdio_mux[port] == EMI1_SLOT2) {
327 sprintf(alias, "phy_sgmii_s2_%x", phy);
328 fdt_set_phy_handle(fdt, compat, addr, alias);
329 fdt_status_okay_by_alias(fdt, "emi1_slot2");
330 } else if (mdio_mux[port] == EMI1_SLOT3) {
331 sprintf(alias, "phy_sgmii_s3_%x", phy);
332 fdt_set_phy_handle(fdt, compat, addr, alias);
333 fdt_status_okay_by_alias(fdt, "emi1_slot3");
334 } else if (mdio_mux[port] == EMI1_SLOT5) {
335 sprintf(alias, "phy_sgmii_s5_%x", phy);
336 fdt_set_phy_handle(fdt, compat, addr, alias);
337 fdt_status_okay_by_alias(fdt, "emi1_slot5");
338 } else if (mdio_mux[port] == EMI1_SLOT6) {
339 sprintf(alias, "phy_sgmii_s6_%x", phy);
340 fdt_set_phy_handle(fdt, compat, addr, alias);
341 fdt_status_okay_by_alias(fdt, "emi1_slot6");
342 } else if (mdio_mux[port] == EMI1_SLOT7) {
343 sprintf(alias, "phy_sgmii_s7_%x", phy);
344 fdt_set_phy_handle(fdt, compat, addr, alias);
345 fdt_status_okay_by_alias(fdt, "emi1_slot7");
353 /* set property for 1000BASE-KX in dtb */
354 off = fdt_node_offset_by_compat_reg(fdt,
355 "fsl,fman-memac-mdio", addr + 0x1000);
356 fdt_setprop_string(fdt, off, "lane-instance", buf);
359 } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
361 case 0x66: /* XFI interface */
367 * if the 10G is XFI, check hwconfig to see what is the
368 * media type, there are two types, fiber or copper,
369 * fix the dtb accordingly.
373 if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
376 fdt_set_phy_handle(fdt, compat, addr,
378 fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio9");
379 sprintf(buf, "%s%s%s", buf, "lane-a,",
380 (char *)lane_mode[1]);
384 if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) {
387 fdt_set_phy_handle(fdt, compat, addr,
389 fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio10");
390 sprintf(buf, "%s%s%s", buf, "lane-b,",
391 (char *)lane_mode[1]);
395 if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g3")) {
398 fdt_set_phy_handle(fdt, compat, addr,
400 fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio1");
401 sprintf(buf, "%s%s%s", buf, "lane-c,",
402 (char *)lane_mode[1]);
406 if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g4")) {
409 fdt_set_phy_handle(fdt, compat, addr,
411 fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio2");
412 sprintf(buf, "%s%s%s", buf, "lane-d,",
413 (char *)lane_mode[1]);
421 phyconn = fdt_getprop(fdt, offset,
422 "phy-connection-type",
424 if (is_backplane_mode(phyconn)) {
425 /* Backplane KR mode: skip fixups */
426 printf("Interface %d in backplane KR mode\n",
429 /* fixed-link for XFI fiber cable */
430 f_link.phy_id = port;
432 f_link.link_speed = 10000;
434 f_link.asym_pause = 0;
435 fdt_delprop(fdt, offset, "phy-handle");
436 fdt_setprop(fdt, offset, "fixed-link",
437 &f_link, sizeof(f_link));
440 /* set property for copper cable */
441 off = fdt_node_offset_by_compat_reg(fdt,
442 "fsl,fman-memac-mdio", addr + 0x1000);
443 fdt_setprop_string(fdt, off,
444 "lane-instance", buf);
453 void fdt_fixup_board_enet(void *fdt)
459 * This function reads RCW to check if Serdes1{A:H} is configured
460 * to slot 1/2/3/4/5/6/7 and update the lane_to_slot[] array accordingly
462 static void initialize_lane_to_slot(void)
464 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
465 u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
466 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
468 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
471 #if defined(CONFIG_TARGET_T2080QDS)
498 #elif defined(CONFIG_TARGET_T2081QDS)
528 int board_eth_init(bd_t *bis)
530 #if defined(CONFIG_FMAN_ENET)
531 int i, idx, lane, slot, interface;
532 struct memac_mdio_info dtsec_mdio_info;
533 struct memac_mdio_info tgec_mdio_info;
534 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
535 u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
538 srds_s1 = in_be32(&gur->rcwsr[4]) &
539 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
540 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
542 initialize_lane_to_slot();
544 /* Initialize the mdio_mux array so we can recognize empty elements */
545 for (i = 0; i < NUM_FM_PORTS; i++)
546 mdio_mux[i] = EMI_NONE;
548 dtsec_mdio_info.regs =
549 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
551 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
553 /* Register the 1G MDIO bus */
554 fm_memac_mdio_init(bis, &dtsec_mdio_info);
556 tgec_mdio_info.regs =
557 (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
558 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
560 /* Register the 10G MDIO bus */
561 fm_memac_mdio_init(bis, &tgec_mdio_info);
563 /* Register the muxing front-ends to the MDIO buses */
564 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
565 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
566 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
567 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
568 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
569 #if defined(CONFIG_TARGET_T2080QDS)
570 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
572 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
573 #if defined(CONFIG_TARGET_T2081QDS)
574 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
575 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
577 t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
579 /* Set the two on-board RGMII PHY address */
580 fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
581 if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
582 FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII)
583 fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
585 fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR);
593 /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot2 */
594 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
595 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
596 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
597 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
598 /* T2080QDS: SGMII in Slot2; T2081QDS: SGMII in Slot1 */
599 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
600 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
608 /* T2080QDS: XAUI/HiGig in Slot3; T2081QDS: in Slot2 */
609 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
610 /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */
611 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
612 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
617 * XFI does not need a PHY to work, but to avoid U-Boot use
618 * default PHY address which is zero to a MAC when it found
619 * a MAC has no PHY address, we give a PHY address to XFI
620 * MAC, and should not use a real XAUI PHY address, since
621 * MDIO can access it successfully, and then MDIO thinks
622 * the XAUI card is used for the XFI MAC, which will cause
625 fm_info_set_phy_address(FM1_10GEC1, 4);
626 fm_info_set_phy_address(FM1_10GEC2, 5);
627 fm_info_set_phy_address(FM1_10GEC3, 6);
628 fm_info_set_phy_address(FM1_10GEC4, 7);
632 fm_info_set_phy_address(FM1_10GEC1, 4);
633 fm_info_set_phy_address(FM1_10GEC2, 5);
634 fm_info_set_phy_address(FM1_10GEC3, 6);
635 fm_info_set_phy_address(FM1_10GEC4, 7);
636 /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */
637 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
638 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
642 fm_info_set_phy_address(FM1_10GEC1, 4);
643 fm_info_set_phy_address(FM1_10GEC2, 5);
644 /* T2080QDS: SGMII in Slot3; T2081QDS: in Slot2 */
645 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
646 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
651 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
652 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
654 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
655 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
663 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
664 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
665 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
666 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
668 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
669 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
675 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
676 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
677 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
678 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
680 #if defined(CONFIG_TARGET_T2080QDS)
685 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
686 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
687 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
689 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
690 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
692 #elif defined(CONFIG_TARGET_T2081QDS)
696 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
697 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
699 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
701 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
703 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
707 /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */
708 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
709 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
710 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
711 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
717 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
718 idx = i - FM1_DTSEC1;
719 interface = fm_info_get_enet_if(i);
721 case PHY_INTERFACE_MODE_SGMII:
722 lane = serdes_get_first_lane(FSL_SRDS_1,
723 SGMII_FM1_DTSEC1 + idx);
726 slot = lane_to_slot[lane];
727 debug("FM1@DTSEC%u expects SGMII in slot %u\n",
729 if (QIXIS_READ(present2) & (1 << (slot - 1)))
734 mdio_mux[i] = EMI1_SLOT1;
735 fm_info_set_mdio(i, mii_dev_for_muxval(
739 mdio_mux[i] = EMI1_SLOT2;
740 fm_info_set_mdio(i, mii_dev_for_muxval(
744 mdio_mux[i] = EMI1_SLOT3;
745 fm_info_set_mdio(i, mii_dev_for_muxval(
748 #if defined(CONFIG_TARGET_T2081QDS)
750 mdio_mux[i] = EMI1_SLOT5;
751 fm_info_set_mdio(i, mii_dev_for_muxval(
755 mdio_mux[i] = EMI1_SLOT6;
756 fm_info_set_mdio(i, mii_dev_for_muxval(
760 mdio_mux[i] = EMI1_SLOT7;
761 fm_info_set_mdio(i, mii_dev_for_muxval(
767 case PHY_INTERFACE_MODE_RGMII:
769 mdio_mux[i] = EMI1_RGMII1;
770 else if (i == FM1_DTSEC4 || FM1_DTSEC10)
771 mdio_mux[i] = EMI1_RGMII2;
772 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
779 for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
780 idx = i - FM1_10GEC1;
781 switch (fm_info_get_enet_if(i)) {
782 case PHY_INTERFACE_MODE_XGMII:
783 if (srds_s1 == 0x51) {
784 lane = serdes_get_first_lane(FSL_SRDS_1,
785 XAUI_FM1_MAC9 + idx);
786 } else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) {
787 lane = serdes_get_first_lane(FSL_SRDS_1,
788 HIGIG_FM1_MAC9 + idx);
790 if (i == FM1_10GEC1 || i == FM1_10GEC2)
791 lane = serdes_get_first_lane(FSL_SRDS_1,
794 lane = serdes_get_first_lane(FSL_SRDS_1,
801 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
803 if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) ||
804 (srds_s1 == 0x6a) || (srds_s1 == 0x70) ||
805 (srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||
807 /* As XFI is in cage intead of a slot, so
808 * ensure doesn't disable the corresponding port
813 slot = lane_to_slot[lane];
814 if (QIXIS_READ(present2) & (1 << (slot - 1)))
823 #endif /* CONFIG_FMAN_ENET */
825 return pci_eth_init(bis);