1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2013 Freescale Semiconductor, Inc.
5 * Shengzhou Liu <Shengzhou.Liu@freescale.com>
12 #include <asm/processor.h>
13 #include <asm/immap_85xx.h>
14 #include <asm/fsl_law.h>
15 #include <asm/fsl_serdes.h>
16 #include <asm/fsl_portals.h>
17 #include <asm/fsl_liodn.h>
23 #include <fsl_dtsec.h>
24 #include <asm/fsl_serdes.h>
26 #include "../common/qixis.h"
27 #include "../common/fman.h"
28 #include "t208xqds_qixis.h"
30 #define EMI_NONE 0xFFFFFFFF
34 #if defined(CONFIG_TARGET_T2080QDS)
40 #elif defined(CONFIG_TARGET_T2081QDS)
49 #define PCCR1_SGMIIA_KX_MASK 0x00008000
50 #define PCCR1_SGMIIB_KX_MASK 0x00004000
51 #define PCCR1_SGMIIC_KX_MASK 0x00002000
52 #define PCCR1_SGMIID_KX_MASK 0x00001000
53 #define PCCR1_SGMIIE_KX_MASK 0x00000800
54 #define PCCR1_SGMIIF_KX_MASK 0x00000400
55 #define PCCR1_SGMIIG_KX_MASK 0x00000200
56 #define PCCR1_SGMIIH_KX_MASK 0x00000100
58 static int mdio_mux[NUM_FM_PORTS];
60 static const char * const mdio_names[] = {
61 #if defined(CONFIG_TARGET_T2080QDS)
62 "T2080QDS_MDIO_RGMII1",
63 "T2080QDS_MDIO_RGMII2",
64 "T2080QDS_MDIO_SLOT1",
65 "T2080QDS_MDIO_SLOT3",
66 "T2080QDS_MDIO_SLOT4",
67 "T2080QDS_MDIO_SLOT5",
68 "T2080QDS_MDIO_SLOT2",
70 #elif defined(CONFIG_TARGET_T2081QDS)
71 "T2081QDS_MDIO_RGMII1",
72 "T2081QDS_MDIO_RGMII2",
73 "T2081QDS_MDIO_SLOT1",
74 "T2081QDS_MDIO_SLOT2",
75 "T2081QDS_MDIO_SLOT3",
76 "T2081QDS_MDIO_SLOT5",
77 "T2081QDS_MDIO_SLOT6",
78 "T2081QDS_MDIO_SLOT7",
83 /* Map SerDes1 8 lanes to default slot, will be initialized dynamically */
84 #if defined(CONFIG_TARGET_T2080QDS)
85 static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1};
86 #elif defined(CONFIG_TARGET_T2081QDS)
87 static u8 lane_to_slot[] = {2, 2, 2, 2, 1, 1, 1, 1};
90 static const char *t208xqds_mdio_name_for_muxval(u8 muxval)
92 return mdio_names[muxval];
95 struct mii_dev *mii_dev_for_muxval(u8 muxval)
98 const char *name = t208xqds_mdio_name_for_muxval(muxval);
101 printf("No bus for muxval %x\n", muxval);
105 bus = miiphy_get_dev_by_name(name);
108 printf("No bus by name %s\n", name);
115 struct t208xqds_mdio {
117 struct mii_dev *realbus;
120 static void t208xqds_mux_mdio(u8 muxval)
124 brdcfg4 = QIXIS_READ(brdcfg[4]);
125 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
126 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
127 QIXIS_WRITE(brdcfg[4], brdcfg4);
131 static int t208xqds_mdio_read(struct mii_dev *bus, int addr, int devad,
134 struct t208xqds_mdio *priv = bus->priv;
136 t208xqds_mux_mdio(priv->muxval);
138 return priv->realbus->read(priv->realbus, addr, devad, regnum);
141 static int t208xqds_mdio_write(struct mii_dev *bus, int addr, int devad,
142 int regnum, u16 value)
144 struct t208xqds_mdio *priv = bus->priv;
146 t208xqds_mux_mdio(priv->muxval);
148 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
151 static int t208xqds_mdio_reset(struct mii_dev *bus)
153 struct t208xqds_mdio *priv = bus->priv;
155 return priv->realbus->reset(priv->realbus);
158 static int t208xqds_mdio_init(char *realbusname, u8 muxval)
160 struct t208xqds_mdio *pmdio;
161 struct mii_dev *bus = mdio_alloc();
164 printf("Failed to allocate t208xqds MDIO bus\n");
168 pmdio = malloc(sizeof(*pmdio));
170 printf("Failed to allocate t208xqds private data\n");
175 bus->read = t208xqds_mdio_read;
176 bus->write = t208xqds_mdio_write;
177 bus->reset = t208xqds_mdio_reset;
178 strcpy(bus->name, t208xqds_mdio_name_for_muxval(muxval));
180 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
182 if (!pmdio->realbus) {
183 printf("No bus with name %s\n", realbusname);
189 pmdio->muxval = muxval;
191 return mdio_register(bus);
194 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
195 enum fm_port port, int offset)
199 char lane_mode[2][20] = {"1000BASE-KX", "10GBASE-KR"};
200 char buf[32] = "serdes-1,";
201 struct fixed_link f_link;
205 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
206 #ifdef CONFIG_TARGET_T2080QDS
207 serdes_corenet_t *srds_regs =
208 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
209 u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1);
211 u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
212 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
214 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
216 if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
217 phy = fm_info_get_phy_address(port);
219 #if defined(CONFIG_TARGET_T2080QDS)
221 if (hwconfig_sub("fsl_1gkx", "fm1_1g1")) {
223 fdt_set_phy_handle(fdt, compat, addr,
225 fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio1");
226 sprintf(buf, "%s%s%s", buf, "lane-c,",
227 (char *)lane_mode[0]);
228 out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
229 PCCR1_SGMIIH_KX_MASK);
233 if (hwconfig_sub("fsl_1gkx", "fm1_1g2")) {
235 fdt_set_phy_handle(fdt, compat, addr,
237 fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio2");
238 sprintf(buf, "%s%s%s", buf, "lane-d,",
239 (char *)lane_mode[0]);
240 out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
241 PCCR1_SGMIIG_KX_MASK);
245 if (hwconfig_sub("fsl_1gkx", "fm1_1g9")) {
247 fdt_set_phy_handle(fdt, compat, addr,
249 fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio9");
250 sprintf(buf, "%s%s%s", buf, "lane-a,",
251 (char *)lane_mode[0]);
252 out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
253 PCCR1_SGMIIE_KX_MASK);
257 if (hwconfig_sub("fsl_1gkx", "fm1_1g10")) {
259 fdt_set_phy_handle(fdt, compat, addr,
261 fdt_status_okay_by_alias(fdt,
263 sprintf(buf, "%s%s%s", buf, "lane-b,",
264 (char *)lane_mode[0]);
265 out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
266 PCCR1_SGMIIF_KX_MASK);
269 if (mdio_mux[port] == EMI1_SLOT2) {
270 sprintf(alias, "phy_sgmii_s2_%x", phy);
271 fdt_set_phy_handle(fdt, compat, addr, alias);
272 fdt_status_okay_by_alias(fdt, "emi1_slot2");
273 } else if (mdio_mux[port] == EMI1_SLOT3) {
274 sprintf(alias, "phy_sgmii_s3_%x", phy);
275 fdt_set_phy_handle(fdt, compat, addr, alias);
276 fdt_status_okay_by_alias(fdt, "emi1_slot3");
280 if (hwconfig_sub("fsl_1gkx", "fm1_1g5")) {
282 fdt_set_phy_handle(fdt, compat, addr,
284 fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio5");
285 sprintf(buf, "%s%s%s", buf, "lane-g,",
286 (char *)lane_mode[0]);
287 out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
288 PCCR1_SGMIIC_KX_MASK);
292 if (hwconfig_sub("fsl_1gkx", "fm1_1g6")) {
294 fdt_set_phy_handle(fdt, compat, addr,
296 fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio6");
297 sprintf(buf, "%s%s%s", buf, "lane-h,",
298 (char *)lane_mode[0]);
299 out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
300 PCCR1_SGMIID_KX_MASK);
303 if (mdio_mux[port] == EMI1_SLOT1) {
304 sprintf(alias, "phy_sgmii_s1_%x", phy);
305 fdt_set_phy_handle(fdt, compat, addr, alias);
306 fdt_status_okay_by_alias(fdt, "emi1_slot1");
307 } else if (mdio_mux[port] == EMI1_SLOT2) {
308 sprintf(alias, "phy_sgmii_s2_%x", phy);
309 fdt_set_phy_handle(fdt, compat, addr, alias);
310 fdt_status_okay_by_alias(fdt, "emi1_slot2");
313 #elif defined(CONFIG_TARGET_T2081QDS)
320 if (mdio_mux[port] == EMI1_SLOT2) {
321 sprintf(alias, "phy_sgmii_s2_%x", phy);
322 fdt_set_phy_handle(fdt, compat, addr, alias);
323 fdt_status_okay_by_alias(fdt, "emi1_slot2");
324 } else if (mdio_mux[port] == EMI1_SLOT3) {
325 sprintf(alias, "phy_sgmii_s3_%x", phy);
326 fdt_set_phy_handle(fdt, compat, addr, alias);
327 fdt_status_okay_by_alias(fdt, "emi1_slot3");
328 } else if (mdio_mux[port] == EMI1_SLOT5) {
329 sprintf(alias, "phy_sgmii_s5_%x", phy);
330 fdt_set_phy_handle(fdt, compat, addr, alias);
331 fdt_status_okay_by_alias(fdt, "emi1_slot5");
332 } else if (mdio_mux[port] == EMI1_SLOT6) {
333 sprintf(alias, "phy_sgmii_s6_%x", phy);
334 fdt_set_phy_handle(fdt, compat, addr, alias);
335 fdt_status_okay_by_alias(fdt, "emi1_slot6");
336 } else if (mdio_mux[port] == EMI1_SLOT7) {
337 sprintf(alias, "phy_sgmii_s7_%x", phy);
338 fdt_set_phy_handle(fdt, compat, addr, alias);
339 fdt_status_okay_by_alias(fdt, "emi1_slot7");
347 /* set property for 1000BASE-KX in dtb */
348 off = fdt_node_offset_by_compat_reg(fdt,
349 "fsl,fman-memac-mdio", addr + 0x1000);
350 fdt_setprop_string(fdt, off, "lane-instance", buf);
353 } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
355 case 0x66: /* XFI interface */
361 * if the 10G is XFI, check hwconfig to see what is the
362 * media type, there are two types, fiber or copper,
363 * fix the dtb accordingly.
367 if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
370 fdt_set_phy_handle(fdt, compat, addr,
372 fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio9");
373 sprintf(buf, "%s%s%s", buf, "lane-a,",
374 (char *)lane_mode[1]);
378 if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) {
381 fdt_set_phy_handle(fdt, compat, addr,
383 fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio10");
384 sprintf(buf, "%s%s%s", buf, "lane-b,",
385 (char *)lane_mode[1]);
389 if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g3")) {
392 fdt_set_phy_handle(fdt, compat, addr,
394 fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio1");
395 sprintf(buf, "%s%s%s", buf, "lane-c,",
396 (char *)lane_mode[1]);
400 if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g4")) {
403 fdt_set_phy_handle(fdt, compat, addr,
405 fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio2");
406 sprintf(buf, "%s%s%s", buf, "lane-d,",
407 (char *)lane_mode[1]);
415 /* fixed-link is used for XFI fiber cable */
416 f_link.phy_id = port;
418 f_link.link_speed = 10000;
420 f_link.asym_pause = 0;
421 fdt_delprop(fdt, offset, "phy-handle");
422 fdt_setprop(fdt, offset, "fixed-link", &f_link,
425 /* set property for copper cable */
426 off = fdt_node_offset_by_compat_reg(fdt,
427 "fsl,fman-memac-mdio", addr + 0x1000);
428 fdt_setprop_string(fdt, off,
429 "lane-instance", buf);
438 void fdt_fixup_board_enet(void *fdt)
444 * This function reads RCW to check if Serdes1{A:H} is configured
445 * to slot 1/2/3/4/5/6/7 and update the lane_to_slot[] array accordingly
447 static void initialize_lane_to_slot(void)
449 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
450 u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
451 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
453 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
456 #if defined(CONFIG_TARGET_T2080QDS)
483 #elif defined(CONFIG_TARGET_T2081QDS)
513 int board_eth_init(bd_t *bis)
515 #if defined(CONFIG_FMAN_ENET)
516 int i, idx, lane, slot, interface;
517 struct memac_mdio_info dtsec_mdio_info;
518 struct memac_mdio_info tgec_mdio_info;
519 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
520 u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
523 srds_s1 = in_be32(&gur->rcwsr[4]) &
524 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
525 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
527 initialize_lane_to_slot();
529 /* Initialize the mdio_mux array so we can recognize empty elements */
530 for (i = 0; i < NUM_FM_PORTS; i++)
531 mdio_mux[i] = EMI_NONE;
533 dtsec_mdio_info.regs =
534 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
536 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
538 /* Register the 1G MDIO bus */
539 fm_memac_mdio_init(bis, &dtsec_mdio_info);
541 tgec_mdio_info.regs =
542 (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
543 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
545 /* Register the 10G MDIO bus */
546 fm_memac_mdio_init(bis, &tgec_mdio_info);
548 /* Register the muxing front-ends to the MDIO buses */
549 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
550 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
551 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
552 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
553 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
554 #if defined(CONFIG_TARGET_T2080QDS)
555 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
557 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
558 #if defined(CONFIG_TARGET_T2081QDS)
559 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
560 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
562 t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
564 /* Set the two on-board RGMII PHY address */
565 fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
566 if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
567 FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII)
568 fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
570 fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR);
578 /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot2 */
579 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
580 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
581 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
582 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
583 /* T2080QDS: SGMII in Slot2; T2081QDS: SGMII in Slot1 */
584 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
585 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
593 /* T2080QDS: XAUI/HiGig in Slot3; T2081QDS: in Slot2 */
594 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
595 /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */
596 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
597 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
602 * XFI does not need a PHY to work, but to avoid U-Boot use
603 * default PHY address which is zero to a MAC when it found
604 * a MAC has no PHY address, we give a PHY address to XFI
605 * MAC, and should not use a real XAUI PHY address, since
606 * MDIO can access it successfully, and then MDIO thinks
607 * the XAUI card is used for the XFI MAC, which will cause
610 fm_info_set_phy_address(FM1_10GEC1, 4);
611 fm_info_set_phy_address(FM1_10GEC2, 5);
612 fm_info_set_phy_address(FM1_10GEC3, 6);
613 fm_info_set_phy_address(FM1_10GEC4, 7);
617 fm_info_set_phy_address(FM1_10GEC1, 4);
618 fm_info_set_phy_address(FM1_10GEC2, 5);
619 fm_info_set_phy_address(FM1_10GEC3, 6);
620 fm_info_set_phy_address(FM1_10GEC4, 7);
621 /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */
622 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
623 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
627 fm_info_set_phy_address(FM1_10GEC1, 4);
628 fm_info_set_phy_address(FM1_10GEC2, 5);
629 /* T2080QDS: SGMII in Slot3; T2081QDS: in Slot2 */
630 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
631 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
636 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
637 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
639 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
640 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
648 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
649 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
650 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
651 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
653 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
654 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
660 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
661 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
662 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
663 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
665 #if defined(CONFIG_TARGET_T2080QDS)
670 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
671 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
672 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
674 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
675 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
677 #elif defined(CONFIG_TARGET_T2081QDS)
681 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
682 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
684 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
686 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
688 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
692 /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */
693 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
694 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
695 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
696 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
702 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
703 idx = i - FM1_DTSEC1;
704 interface = fm_info_get_enet_if(i);
706 case PHY_INTERFACE_MODE_SGMII:
707 lane = serdes_get_first_lane(FSL_SRDS_1,
708 SGMII_FM1_DTSEC1 + idx);
711 slot = lane_to_slot[lane];
712 debug("FM1@DTSEC%u expects SGMII in slot %u\n",
714 if (QIXIS_READ(present2) & (1 << (slot - 1)))
719 mdio_mux[i] = EMI1_SLOT1;
720 fm_info_set_mdio(i, mii_dev_for_muxval(
724 mdio_mux[i] = EMI1_SLOT2;
725 fm_info_set_mdio(i, mii_dev_for_muxval(
729 mdio_mux[i] = EMI1_SLOT3;
730 fm_info_set_mdio(i, mii_dev_for_muxval(
733 #if defined(CONFIG_TARGET_T2081QDS)
735 mdio_mux[i] = EMI1_SLOT5;
736 fm_info_set_mdio(i, mii_dev_for_muxval(
740 mdio_mux[i] = EMI1_SLOT6;
741 fm_info_set_mdio(i, mii_dev_for_muxval(
745 mdio_mux[i] = EMI1_SLOT7;
746 fm_info_set_mdio(i, mii_dev_for_muxval(
752 case PHY_INTERFACE_MODE_RGMII:
754 mdio_mux[i] = EMI1_RGMII1;
755 else if (i == FM1_DTSEC4 || FM1_DTSEC10)
756 mdio_mux[i] = EMI1_RGMII2;
757 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
764 for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
765 idx = i - FM1_10GEC1;
766 switch (fm_info_get_enet_if(i)) {
767 case PHY_INTERFACE_MODE_XGMII:
768 if (srds_s1 == 0x51) {
769 lane = serdes_get_first_lane(FSL_SRDS_1,
770 XAUI_FM1_MAC9 + idx);
771 } else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) {
772 lane = serdes_get_first_lane(FSL_SRDS_1,
773 HIGIG_FM1_MAC9 + idx);
775 if (i == FM1_10GEC1 || i == FM1_10GEC2)
776 lane = serdes_get_first_lane(FSL_SRDS_1,
779 lane = serdes_get_first_lane(FSL_SRDS_1,
786 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
788 if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) ||
789 (srds_s1 == 0x6a) || (srds_s1 == 0x70) ||
790 (srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||
792 /* As XFI is in cage intead of a slot, so
793 * ensure doesn't disable the corresponding port
798 slot = lane_to_slot[lane];
799 if (QIXIS_READ(present2) & (1 << (slot - 1)))
808 #endif /* CONFIG_FMAN_ENET */
810 return pci_eth_init(bis);