board/freescale/t208xqds/eth_t208xqds.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2013 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  *
   6  * Shengzhou Liu <Shengzhou.Liu@freescale.com>
   7  */
   8
   9 #include <common.h>
  10 #include <command.h>
  11 #include <fdt_support.h>
  12 #include <log.h>
  13 #include <net.h>
  14 #include <netdev.h>
  15 #include <asm/mmu.h>
  16 #include <asm/processor.h>
  17 #include <asm/immap_85xx.h>
  18 #include <asm/fsl_law.h>
  19 #include <asm/fsl_serdes.h>
  20 #include <asm/fsl_portals.h>
  21 #include <asm/fsl_liodn.h>
  22 #include <malloc.h>
  23 #include <fm_eth.h>
  24 #include <fsl_mdio.h>
  25 #include <miiphy.h>
  26 #include <phy.h>
  27 #include <fsl_dtsec.h>
  28 #include <asm/fsl_serdes.h>
  29 #include <hwconfig.h>
  30 #include "../common/qixis.h"
  31 #include "../common/fman.h"
  32 #include "t208xqds_qixis.h"
  33 #include <linux/libfdt.h>
  34
  35 #define EMI_NONE        0xFFFFFFFF
  36 #define EMI1_RGMII1     0
  37 #define EMI1_RGMII2     1
  38 #define EMI1_SLOT1      2
  39 #if defined(CONFIG_TARGET_T2080QDS)
  40 #define EMI1_SLOT2      6
  41 #define EMI1_SLOT3      3
  42 #define EMI1_SLOT4      4
  43 #define EMI1_SLOT5      5
  44 #define EMI2            7
  45 #elif defined(CONFIG_TARGET_T2081QDS)
  46 #define EMI1_SLOT2      3
  47 #define EMI1_SLOT3      4
  48 #define EMI1_SLOT5      5
  49 #define EMI1_SLOT6      6
  50 #define EMI1_SLOT7      7
  51 #define EMI2            8
  52 #endif
  53
  54 #define PCCR1_SGMIIA_KX_MASK            0x00008000
  55 #define PCCR1_SGMIIB_KX_MASK            0x00004000
  56 #define PCCR1_SGMIIC_KX_MASK            0x00002000
  57 #define PCCR1_SGMIID_KX_MASK            0x00001000
  58 #define PCCR1_SGMIIE_KX_MASK            0x00000800
  59 #define PCCR1_SGMIIF_KX_MASK            0x00000400
  60 #define PCCR1_SGMIIG_KX_MASK            0x00000200
  61 #define PCCR1_SGMIIH_KX_MASK            0x00000100
  62
  63 static int mdio_mux[NUM_FM_PORTS];
  64
  65 static const char * const mdio_names[] = {
  66 #if defined(CONFIG_TARGET_T2080QDS)
  67         "T2080QDS_MDIO_RGMII1",
  68         "T2080QDS_MDIO_RGMII2",
  69         "T2080QDS_MDIO_SLOT1",
  70         "T2080QDS_MDIO_SLOT3",
  71         "T2080QDS_MDIO_SLOT4",
  72         "T2080QDS_MDIO_SLOT5",
  73         "T2080QDS_MDIO_SLOT2",
  74         "T2080QDS_MDIO_10GC",
  75 #elif defined(CONFIG_TARGET_T2081QDS)
  76         "T2081QDS_MDIO_RGMII1",
  77         "T2081QDS_MDIO_RGMII2",
  78         "T2081QDS_MDIO_SLOT1",
  79         "T2081QDS_MDIO_SLOT2",
  80         "T2081QDS_MDIO_SLOT3",
  81         "T2081QDS_MDIO_SLOT5",
  82         "T2081QDS_MDIO_SLOT6",
  83         "T2081QDS_MDIO_SLOT7",
  84         "T2081QDS_MDIO_10GC",
  85 #endif
  86 };
  87
  88 /* Map SerDes1 8 lanes to default slot, will be initialized dynamically */
  89 #if defined(CONFIG_TARGET_T2080QDS)
  90 static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1};
  91 #elif defined(CONFIG_TARGET_T2081QDS)
  92 static u8 lane_to_slot[] = {2, 2, 2, 2, 1, 1, 1, 1};
  93 #endif
  94
  95 static const char *t208xqds_mdio_name_for_muxval(u8 muxval)
  96 {
  97         return mdio_names[muxval];
  98 }
  99
 100 struct mii_dev *mii_dev_for_muxval(u8 muxval)
 101 {
 102         struct mii_dev *bus;
 103         const char *name = t208xqds_mdio_name_for_muxval(muxval);
 104
 105         if (!name) {
 106                 printf("No bus for muxval %x\n", muxval);
 107                 return NULL;
 108         }
 109
 110         bus = miiphy_get_dev_by_name(name);
 111
 112         if (!bus) {
 113                 printf("No bus by name %s\n", name);
 114                 return NULL;
 115         }
 116
 117         return bus;
 118 }
 119
 120 struct t208xqds_mdio {
 121         u8 muxval;
 122         struct mii_dev *realbus;
 123 };
 124
 125 static void t208xqds_mux_mdio(u8 muxval)
 126 {
 127         u8 brdcfg4;
 128         if (muxval < 8) {
 129                 brdcfg4 = QIXIS_READ(brdcfg[4]);
 130                 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
 131                 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
 132                 QIXIS_WRITE(brdcfg[4], brdcfg4);
 133         }
 134 }
 135
 136 static int t208xqds_mdio_read(struct mii_dev *bus, int addr, int devad,
 137                                 int regnum)
 138 {
 139         struct t208xqds_mdio *priv = bus->priv;
 140
 141         t208xqds_mux_mdio(priv->muxval);
 142
 143         return priv->realbus->read(priv->realbus, addr, devad, regnum);
 144 }
 145
 146 static int t208xqds_mdio_write(struct mii_dev *bus, int addr, int devad,
 147                                 int regnum, u16 value)
 148 {
 149         struct t208xqds_mdio *priv = bus->priv;
 150
 151         t208xqds_mux_mdio(priv->muxval);
 152
 153         return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
 154 }
 155
 156 static int t208xqds_mdio_reset(struct mii_dev *bus)
 157 {
 158         struct t208xqds_mdio *priv = bus->priv;
 159
 160         return priv->realbus->reset(priv->realbus);
 161 }
 162
 163 static int t208xqds_mdio_init(char *realbusname, u8 muxval)
 164 {
 165         struct t208xqds_mdio *pmdio;
 166         struct mii_dev *bus = mdio_alloc();
 167
 168         if (!bus) {
 169                 printf("Failed to allocate t208xqds MDIO bus\n");
 170                 return -1;
 171         }
 172
 173         pmdio = malloc(sizeof(*pmdio));
 174         if (!pmdio) {
 175                 printf("Failed to allocate t208xqds private data\n");
 176                 free(bus);
 177                 return -1;
 178         }
 179
 180         bus->read = t208xqds_mdio_read;
 181         bus->write = t208xqds_mdio_write;
 182         bus->reset = t208xqds_mdio_reset;
 183         strcpy(bus->name, t208xqds_mdio_name_for_muxval(muxval));
 184
 185         pmdio->realbus = miiphy_get_dev_by_name(realbusname);
 186
 187         if (!pmdio->realbus) {
 188                 printf("No bus with name %s\n", realbusname);
 189                 free(bus);
 190                 free(pmdio);
 191                 return -1;
 192         }
 193
 194         pmdio->muxval = muxval;
 195         bus->priv = pmdio;
 196         return mdio_register(bus);
 197 }
 198
 199 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 200                                 enum fm_port port, int offset)
 201 {
 202         int phy;
 203         char alias[20];
 204         char lane_mode[2][20] = {"1000BASE-KX", "10GBASE-KR"};
 205         char buf[32] = "serdes-1,";
 206         struct fixed_link f_link;
 207         int media_type = 0;
 208         const char *phyconn;
 209         int off;
 210
 211         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 212 #ifdef CONFIG_TARGET_T2080QDS
 213         serdes_corenet_t *srds_regs =
 214                 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
 215         u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1);
 216 #endif
 217         u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
 218                                 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 219
 220         srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 221
 222         if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
 223                 phy = fm_info_get_phy_address(port);
 224                 switch (port) {
 225 #if defined(CONFIG_TARGET_T2080QDS)
 226                 case FM1_DTSEC1:
 227                         if (hwconfig_sub("fsl_1gkx", "fm1_1g1")) {
 228                                 media_type = 1;
 229                                 fdt_set_phy_handle(fdt, compat, addr,
 230                                                    "phy_1gkx1");
 231                                 fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio1");
 232                                 sprintf(buf, "%s%s%s", buf, "lane-c,",
 233                                                 (char *)lane_mode[0]);
 234                                 out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
 235                                          PCCR1_SGMIIH_KX_MASK);
 236                                 break;
 237                         }
 238                 case FM1_DTSEC2:
 239                         if (hwconfig_sub("fsl_1gkx", "fm1_1g2")) {
 240                                 media_type = 1;
 241                                 fdt_set_phy_handle(fdt, compat, addr,
 242                                                    "phy_1gkx2");
 243                                 fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio2");
 244                                 sprintf(buf, "%s%s%s", buf, "lane-d,",
 245                                                 (char *)lane_mode[0]);
 246                                 out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
 247                                          PCCR1_SGMIIG_KX_MASK);
 248                                 break;
 249                         }
 250                 case FM1_DTSEC9:
 251                         if (hwconfig_sub("fsl_1gkx", "fm1_1g9")) {
 252                                 media_type = 1;
 253                                 fdt_set_phy_handle(fdt, compat, addr,
 254                                                    "phy_1gkx9");
 255                                 fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio9");
 256                                 sprintf(buf, "%s%s%s", buf, "lane-a,",
 257                                                 (char *)lane_mode[0]);
 258                                 out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
 259                                          PCCR1_SGMIIE_KX_MASK);
 260                                 break;
 261                         }
 262                 case FM1_DTSEC10:
 263                         if (hwconfig_sub("fsl_1gkx", "fm1_1g10")) {
 264                                 media_type = 1;
 265                                 fdt_set_phy_handle(fdt, compat, addr,
 266                                                    "phy_1gkx10");
 267                                 fdt_status_okay_by_alias(fdt,
 268                                                          "1gkx_pcs_mdio10");
 269                                 sprintf(buf, "%s%s%s", buf, "lane-b,",
 270                                                 (char *)lane_mode[0]);
 271                                 out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
 272                                          PCCR1_SGMIIF_KX_MASK);
 273                                 break;
 274                         }
 275                         if (mdio_mux[port] == EMI1_SLOT2) {
 276                                 sprintf(alias, "phy_sgmii_s2_%x", phy);
 277                                 fdt_set_phy_handle(fdt, compat, addr, alias);
 278                                 fdt_status_okay_by_alias(fdt, "emi1_slot2");
 279                         } else if (mdio_mux[port] == EMI1_SLOT3) {
 280                                 sprintf(alias, "phy_sgmii_s3_%x", phy);
 281                                 fdt_set_phy_handle(fdt, compat, addr, alias);
 282                                 fdt_status_okay_by_alias(fdt, "emi1_slot3");
 283                         }
 284                         break;
 285                 case FM1_DTSEC5:
 286                         if (hwconfig_sub("fsl_1gkx", "fm1_1g5")) {
 287                                 media_type = 1;
 288                                 fdt_set_phy_handle(fdt, compat, addr,
 289                                                    "phy_1gkx5");
 290                                 fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio5");
 291                                 sprintf(buf, "%s%s%s", buf, "lane-g,",
 292                                                 (char *)lane_mode[0]);
 293                                 out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
 294                                          PCCR1_SGMIIC_KX_MASK);
 295                                 break;
 296                         }
 297                 case FM1_DTSEC6:
 298                         if (hwconfig_sub("fsl_1gkx", "fm1_1g6")) {
 299                                 media_type = 1;
 300                                 fdt_set_phy_handle(fdt, compat, addr,
 301                                                    "phy_1gkx6");
 302                                 fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio6");
 303                                 sprintf(buf, "%s%s%s", buf, "lane-h,",
 304                                                 (char *)lane_mode[0]);
 305                                 out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
 306                                          PCCR1_SGMIID_KX_MASK);
 307                                 break;
 308                         }
 309                         if (mdio_mux[port] == EMI1_SLOT1) {
 310                                 sprintf(alias, "phy_sgmii_s1_%x", phy);
 311                                 fdt_set_phy_handle(fdt, compat, addr, alias);
 312                                 fdt_status_okay_by_alias(fdt, "emi1_slot1");
 313                         } else if (mdio_mux[port] == EMI1_SLOT2) {
 314                                 sprintf(alias, "phy_sgmii_s2_%x", phy);
 315                                 fdt_set_phy_handle(fdt, compat, addr, alias);
 316                                 fdt_status_okay_by_alias(fdt, "emi1_slot2");
 317                         }
 318                         break;
 319 #elif defined(CONFIG_TARGET_T2081QDS)
 320                 case FM1_DTSEC1:
 321                 case FM1_DTSEC2:
 322                 case FM1_DTSEC5:
 323                 case FM1_DTSEC6:
 324                 case FM1_DTSEC9:
 325                 case FM1_DTSEC10:
 326                         if (mdio_mux[port] == EMI1_SLOT2) {
 327                                 sprintf(alias, "phy_sgmii_s2_%x", phy);
 328                                 fdt_set_phy_handle(fdt, compat, addr, alias);
 329                                 fdt_status_okay_by_alias(fdt, "emi1_slot2");
 330                         } else if (mdio_mux[port] == EMI1_SLOT3) {
 331                                 sprintf(alias, "phy_sgmii_s3_%x", phy);
 332                                 fdt_set_phy_handle(fdt, compat, addr, alias);
 333                                 fdt_status_okay_by_alias(fdt, "emi1_slot3");
 334                         } else if (mdio_mux[port] == EMI1_SLOT5) {
 335                                 sprintf(alias, "phy_sgmii_s5_%x", phy);
 336                                 fdt_set_phy_handle(fdt, compat, addr, alias);
 337                                 fdt_status_okay_by_alias(fdt, "emi1_slot5");
 338                         } else if (mdio_mux[port] == EMI1_SLOT6) {
 339                                 sprintf(alias, "phy_sgmii_s6_%x", phy);
 340                                 fdt_set_phy_handle(fdt, compat, addr, alias);
 341                                 fdt_status_okay_by_alias(fdt, "emi1_slot6");
 342                         } else if (mdio_mux[port] == EMI1_SLOT7) {
 343                                 sprintf(alias, "phy_sgmii_s7_%x", phy);
 344                                 fdt_set_phy_handle(fdt, compat, addr, alias);
 345                                 fdt_status_okay_by_alias(fdt, "emi1_slot7");
 346                         }
 347                         break;
 348 #endif
 349                 default:
 350                         break;
 351                 }
 352                 if (media_type) {
 353                         /* set property for 1000BASE-KX in dtb */
 354                         off = fdt_node_offset_by_compat_reg(fdt,
 355                                         "fsl,fman-memac-mdio", addr + 0x1000);
 356                         fdt_setprop_string(fdt, off, "lane-instance", buf);
 357                 }
 358
 359         } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
 360                 switch (srds_s1) {
 361                 case 0x66: /* XFI interface */
 362                 case 0x6b:
 363                 case 0x6c:
 364                 case 0x6d:
 365                 case 0x71:
 366                         /*
 367                         * if the 10G is XFI, check hwconfig to see what is the
 368                         * media type, there are two types, fiber or copper,
 369                         * fix the dtb accordingly.
 370                         */
 371                         switch (port) {
 372                         case FM1_10GEC1:
 373                         if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
 374                                 /* it's MAC9 */
 375                                 media_type = 1;
 376                                 fdt_set_phy_handle(fdt, compat, addr,
 377                                                 "phy_xfi9");
 378                                 fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio9");
 379                                 sprintf(buf, "%s%s%s", buf, "lane-a,",
 380                                                 (char *)lane_mode[1]);
 381                         }
 382                                 break;
 383                         case FM1_10GEC2:
 384                         if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) {
 385                                 /* it's MAC10 */
 386                                 media_type = 1;
 387                                 fdt_set_phy_handle(fdt, compat, addr,
 388                                                 "phy_xfi10");
 389                                 fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio10");
 390                                 sprintf(buf, "%s%s%s", buf, "lane-b,",
 391                                                 (char *)lane_mode[1]);
 392                         }
 393                                 break;
 394                         case FM1_10GEC3:
 395                         if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g3")) {
 396                                 /* it's MAC1 */
 397                                 media_type = 1;
 398                                 fdt_set_phy_handle(fdt, compat, addr,
 399                                                 "phy_xfi1");
 400                                 fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio1");
 401                                 sprintf(buf, "%s%s%s", buf, "lane-c,",
 402                                                 (char *)lane_mode[1]);
 403                         }
 404                                 break;
 405                         case FM1_10GEC4:
 406                         if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g4")) {
 407                                 /* it's MAC2 */
 408                                 media_type = 1;
 409                                 fdt_set_phy_handle(fdt, compat, addr,
 410                                                 "phy_xfi2");
 411                                 fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio2");
 412                                 sprintf(buf, "%s%s%s", buf, "lane-d,",
 413                                                 (char *)lane_mode[1]);
 414                         }
 415                                 break;
 416                         default:
 417                                 return;
 418                         }
 419
 420                         if (!media_type) {
 421                                 phyconn = fdt_getprop(fdt, offset,
 422                                                       "phy-connection-type",
 423                                                       NULL);
 424                                 if (is_backplane_mode(phyconn)) {
 425                                         /* Backplane KR mode: skip fixups */
 426                                         printf("Interface %d in backplane KR mode\n",
 427                                                port);
 428                                 } else {
 429                                         /* fixed-link for XFI fiber cable */
 430                                         f_link.phy_id = port;
 431                                         f_link.duplex = 1;
 432                                         f_link.link_speed = 10000;
 433                                         f_link.pause = 0;
 434                                         f_link.asym_pause = 0;
 435                                         fdt_delprop(fdt, offset, "phy-handle");
 436                                         fdt_setprop(fdt, offset, "fixed-link",
 437                                                     &f_link, sizeof(f_link));
 438                                 }
 439                         } else {
 440                                 /* set property for copper cable */
 441                                 off = fdt_node_offset_by_compat_reg(fdt,
 442                                         "fsl,fman-memac-mdio", addr + 0x1000);
 443                                 fdt_setprop_string(fdt, off,
 444                                         "lane-instance", buf);
 445                         }
 446                         break;
 447                 default:
 448                         break;
 449                 }
 450         }
 451 }
 452
 453 void fdt_fixup_board_enet(void *fdt)
 454 {
 455         return;
 456 }
 457
 458 /*
 459  * This function reads RCW to check if Serdes1{A:H} is configured
 460  * to slot 1/2/3/4/5/6/7 and update the lane_to_slot[] array accordingly
 461  */
 462 static void initialize_lane_to_slot(void)
 463 {
 464         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 465         u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
 466                                 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 467
 468         srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 469
 470         switch (srds_s1) {
 471 #if defined(CONFIG_TARGET_T2080QDS)
 472         case 0x51:
 473         case 0x5f:
 474         case 0x65:
 475         case 0x6b:
 476         case 0x71:
 477                 lane_to_slot[5] = 2;
 478                 lane_to_slot[6] = 2;
 479                 lane_to_slot[7] = 2;
 480                 break;
 481         case 0xa6:
 482         case 0x8e:
 483         case 0x8f:
 484         case 0x82:
 485         case 0x83:
 486         case 0xd3:
 487         case 0xd9:
 488         case 0xcb:
 489                 lane_to_slot[6] = 2;
 490                 lane_to_slot[7] = 2;
 491                 break;
 492         case 0xda:
 493                 lane_to_slot[4] = 3;
 494                 lane_to_slot[5] = 3;
 495                 lane_to_slot[6] = 3;
 496                 lane_to_slot[7] = 3;
 497                 break;
 498 #elif defined(CONFIG_TARGET_T2081QDS)
 499         case 0x6b:
 500                 lane_to_slot[4] = 1;
 501                 lane_to_slot[5] = 3;
 502                 lane_to_slot[6] = 3;
 503                 lane_to_slot[7] = 3;
 504                 break;
 505         case 0xca:
 506         case 0xcb:
 507                 lane_to_slot[1] = 7;
 508                 lane_to_slot[2] = 6;
 509                 lane_to_slot[3] = 5;
 510                 lane_to_slot[5] = 3;
 511                 lane_to_slot[6] = 3;
 512                 lane_to_slot[7] = 3;
 513                 break;
 514         case 0xf2:
 515                 lane_to_slot[1] = 7;
 516                 lane_to_slot[2] = 7;
 517                 lane_to_slot[3] = 7;
 518                 lane_to_slot[5] = 4;
 519                 lane_to_slot[6] = 3;
 520                 lane_to_slot[7] = 7;
 521                 break;
 522 #endif
 523         default:
 524                 break;
 525         }
 526 }
 527
 528 int board_eth_init(struct bd_info *bis)
 529 {
 530 #if defined(CONFIG_FMAN_ENET)
 531         int i, idx, lane, slot, interface;
 532         struct memac_mdio_info dtsec_mdio_info;
 533         struct memac_mdio_info tgec_mdio_info;
 534         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 535         u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
 536         u32 srds_s1;
 537
 538         srds_s1 = in_be32(&gur->rcwsr[4]) &
 539                                         FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 540         srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 541
 542         initialize_lane_to_slot();
 543
 544         /* Initialize the mdio_mux array so we can recognize empty elements */
 545         for (i = 0; i < NUM_FM_PORTS; i++)
 546                 mdio_mux[i] = EMI_NONE;
 547
 548         dtsec_mdio_info.regs =
 549                 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
 550
 551         dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 552
 553         /* Register the 1G MDIO bus */
 554         fm_memac_mdio_init(bis, &dtsec_mdio_info);
 555
 556         tgec_mdio_info.regs =
 557                 (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
 558         tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
 559
 560         /* Register the 10G MDIO bus */
 561         fm_memac_mdio_init(bis, &tgec_mdio_info);
 562
 563         /* Register the muxing front-ends to the MDIO buses */
 564         t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
 565         t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
 566         t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
 567         t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
 568         t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
 569 #if defined(CONFIG_TARGET_T2080QDS)
 570         t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
 571 #endif
 572         t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
 573 #if defined(CONFIG_TARGET_T2081QDS)
 574         t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
 575         t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
 576 #endif
 577         t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
 578
 579         /* Set the two on-board RGMII PHY address */
 580         fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
 581         if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
 582                         FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII)
 583                 fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
 584         else
 585                 fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR);
 586
 587         switch (srds_s1) {
 588         case 0x1b:
 589         case 0x1c:
 590         case 0x95:
 591         case 0xa2:
 592         case 0x94:
 593                 /* T2080QDS: SGMII in Slot3;  T2081QDS: SGMII in Slot2 */
 594                 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
 595                 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
 596                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
 597                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
 598                 /* T2080QDS: SGMII in Slot2;  T2081QDS: SGMII in Slot1 */
 599                 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
 600                 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
 601                 break;
 602         case 0x50:
 603         case 0x51:
 604         case 0x5e:
 605         case 0x5f:
 606         case 0x64:
 607         case 0x65:
 608                 /* T2080QDS: XAUI/HiGig in Slot3;  T2081QDS: in Slot2 */
 609                 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
 610                 /* T2080QDS: SGMII in Slot2;  T2081QDS: in Slot3 */
 611                 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
 612                 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
 613                 break;
 614         case 0x66:
 615         case 0x67:
 616                 /*
 617                  * XFI does not need a PHY to work, but to avoid U-Boot use
 618                  * default PHY address which is zero to a MAC when it found
 619                  * a MAC has no PHY address, we give a PHY address to XFI
 620                  * MAC, and should not use a real XAUI PHY address, since
 621                  * MDIO can access it successfully, and then MDIO thinks
 622                  * the XAUI card is used for the XFI MAC, which will cause
 623                  * error.
 624                  */
 625                 fm_info_set_phy_address(FM1_10GEC1, 4);
 626                 fm_info_set_phy_address(FM1_10GEC2, 5);
 627                 fm_info_set_phy_address(FM1_10GEC3, 6);
 628                 fm_info_set_phy_address(FM1_10GEC4, 7);
 629                 break;
 630         case 0x6a:
 631         case 0x6b:
 632                 fm_info_set_phy_address(FM1_10GEC1, 4);
 633                 fm_info_set_phy_address(FM1_10GEC2, 5);
 634                 fm_info_set_phy_address(FM1_10GEC3, 6);
 635                 fm_info_set_phy_address(FM1_10GEC4, 7);
 636                 /* T2080QDS: SGMII in Slot2;  T2081QDS: in Slot3 */
 637                 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
 638                 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
 639                 break;
 640         case 0x6c:
 641         case 0x6d:
 642                 fm_info_set_phy_address(FM1_10GEC1, 4);
 643                 fm_info_set_phy_address(FM1_10GEC2, 5);
 644                 /* T2080QDS: SGMII in Slot3;  T2081QDS: in Slot2 */
 645                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
 646                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
 647                 break;
 648         case 0x70:
 649         case 0x71:
 650                 /* SGMII in Slot3 */
 651                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
 652                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
 653                 /* SGMII in Slot2 */
 654                 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
 655                 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
 656                 break;
 657         case 0xa6:
 658         case 0x8e:
 659         case 0x8f:
 660         case 0x82:
 661         case 0x83:
 662                 /* SGMII in Slot3 */
 663                 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
 664                 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
 665                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
 666                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
 667                 /* SGMII in Slot2 */
 668                 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
 669                 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
 670                 break;
 671         case 0xa4:
 672         case 0x96:
 673         case 0x8a:
 674                 /* SGMII in Slot3 */
 675                 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
 676                 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
 677                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
 678                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
 679                 break;
 680 #if defined(CONFIG_TARGET_T2080QDS)
 681         case 0xd9:
 682         case 0xd3:
 683         case 0xcb:
 684                 /* SGMII in Slot3 */
 685                 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
 686                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
 687                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
 688                 /* SGMII in Slot2 */
 689                 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
 690                 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
 691                 break;
 692 #elif defined(CONFIG_TARGET_T2081QDS)
 693         case 0xca:
 694         case 0xcb:
 695                 /* SGMII in Slot3 */
 696                 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
 697                 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
 698                 /* SGMII in Slot5 */
 699                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
 700                 /* SGMII in Slot6 */
 701                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
 702                 /* SGMII in Slot7 */
 703                 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
 704                 break;
 705 #endif
 706         case 0xf2:
 707                 /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */
 708                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
 709                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
 710                 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
 711                 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
 712                 break;
 713         default:
 714                 break;
 715         }
 716
 717         for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
 718                 idx = i - FM1_DTSEC1;
 719                 interface = fm_info_get_enet_if(i);
 720                 switch (interface) {
 721                 case PHY_INTERFACE_MODE_SGMII:
 722                         lane = serdes_get_first_lane(FSL_SRDS_1,
 723                                         SGMII_FM1_DTSEC1 + idx);
 724                         if (lane < 0)
 725                                 break;
 726                         slot = lane_to_slot[lane];
 727                         debug("FM1@DTSEC%u expects SGMII in slot %u\n",
 728                               idx + 1, slot);
 729                         if (QIXIS_READ(present2) & (1 << (slot - 1)))
 730                                 fm_disable_port(i);
 731
 732                         switch (slot) {
 733                         case 1:
 734                                 mdio_mux[i] = EMI1_SLOT1;
 735                                 fm_info_set_mdio(i, mii_dev_for_muxval(
 736                                                  mdio_mux[i]));
 737                                 break;
 738                         case 2:
 739                                 mdio_mux[i] = EMI1_SLOT2;
 740                                 fm_info_set_mdio(i, mii_dev_for_muxval(
 741                                                  mdio_mux[i]));
 742                                 break;
 743                         case 3:
 744                                 mdio_mux[i] = EMI1_SLOT3;
 745                                 fm_info_set_mdio(i, mii_dev_for_muxval(
 746                                                  mdio_mux[i]));
 747                                 break;
 748 #if defined(CONFIG_TARGET_T2081QDS)
 749                         case 5:
 750                                 mdio_mux[i] = EMI1_SLOT5;
 751                                 fm_info_set_mdio(i, mii_dev_for_muxval(
 752                                                  mdio_mux[i]));
 753                                 break;
 754                         case 6:
 755                                 mdio_mux[i] = EMI1_SLOT6;
 756                                 fm_info_set_mdio(i, mii_dev_for_muxval(
 757                                                  mdio_mux[i]));
 758                                 break;
 759                         case 7:
 760                                 mdio_mux[i] = EMI1_SLOT7;
 761                                 fm_info_set_mdio(i, mii_dev_for_muxval(
 762                                                  mdio_mux[i]));
 763                                 break;
 764 #endif
 765                         }
 766                         break;
 767                 case PHY_INTERFACE_MODE_RGMII:
 768                         if (i == FM1_DTSEC3)
 769                                 mdio_mux[i] = EMI1_RGMII1;
 770                         else if (i == FM1_DTSEC4 || FM1_DTSEC10)
 771                                 mdio_mux[i] = EMI1_RGMII2;
 772                         fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 773                         break;
 774                 default:
 775                         break;
 776                 }
 777         }
 778
 779         for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
 780                 idx = i - FM1_10GEC1;
 781                 switch (fm_info_get_enet_if(i)) {
 782                 case PHY_INTERFACE_MODE_XGMII:
 783                         if (srds_s1 == 0x51) {
 784                                 lane = serdes_get_first_lane(FSL_SRDS_1,
 785                                                 XAUI_FM1_MAC9 + idx);
 786                         } else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) {
 787                                 lane = serdes_get_first_lane(FSL_SRDS_1,
 788                                                 HIGIG_FM1_MAC9 + idx);
 789                         } else {
 790                                 if (i == FM1_10GEC1 || i == FM1_10GEC2)
 791                                         lane = serdes_get_first_lane(FSL_SRDS_1,
 792                                                 XFI_FM1_MAC9 + idx);
 793                                 else
 794                                         lane = serdes_get_first_lane(FSL_SRDS_1,
 795                                                 XFI_FM1_MAC1 + idx);
 796                         }
 797
 798                         if (lane < 0)
 799                                 break;
 800                         mdio_mux[i] = EMI2;
 801                         fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 802
 803                         if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) ||
 804                             (srds_s1 == 0x6a) || (srds_s1 == 0x70) ||
 805                             (srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||
 806                             (srds_s1 == 0x71)) {
 807                                 /* As XFI is in cage intead of a slot, so
 808                                  * ensure doesn't disable the corresponding port
 809                                  */
 810                                 break;
 811                         }
 812
 813                         slot = lane_to_slot[lane];
 814                         if (QIXIS_READ(present2) & (1 << (slot - 1)))
 815                                 fm_disable_port(i);
 816                         break;
 817                 default:
 818                         break;
 819                 }
 820         }
 821
 822         cpu_eth_init(bis);
 823 #endif /* CONFIG_FMAN_ENET */
 824
 825         return pci_eth_init(bis);
 826 }