board/freescale/t208xqds/eth_t208xqds.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2013 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  *
   6  * Shengzhou Liu <Shengzhou.Liu@freescale.com>
   7  */
   8
   9 #include <common.h>
  10 #include <command.h>
  11 #include <fdt_support.h>
  12 #include <net.h>
  13 #include <netdev.h>
  14 #include <asm/mmu.h>
  15 #include <asm/processor.h>
  16 #include <asm/immap_85xx.h>
  17 #include <asm/fsl_law.h>
  18 #include <asm/fsl_serdes.h>
  19 #include <asm/fsl_portals.h>
  20 #include <asm/fsl_liodn.h>
  21 #include <malloc.h>
  22 #include <fm_eth.h>
  23 #include <fsl_mdio.h>
  24 #include <miiphy.h>
  25 #include <phy.h>
  26 #include <fsl_dtsec.h>
  27 #include <asm/fsl_serdes.h>
  28 #include <hwconfig.h>
  29 #include "../common/qixis.h"
  30 #include "../common/fman.h"
  31 #include "t208xqds_qixis.h"
  32 #include <linux/libfdt.h>
  33
  34 #define EMI_NONE        0xFFFFFFFF
  35 #define EMI1_RGMII1     0
  36 #define EMI1_RGMII2     1
  37 #define EMI1_SLOT1      2
  38 #if defined(CONFIG_TARGET_T2080QDS)
  39 #define EMI1_SLOT2      6
  40 #define EMI1_SLOT3      3
  41 #define EMI1_SLOT4      4
  42 #define EMI1_SLOT5      5
  43 #define EMI2            7
  44 #elif defined(CONFIG_TARGET_T2081QDS)
  45 #define EMI1_SLOT2      3
  46 #define EMI1_SLOT3      4
  47 #define EMI1_SLOT5      5
  48 #define EMI1_SLOT6      6
  49 #define EMI1_SLOT7      7
  50 #define EMI2            8
  51 #endif
  52
  53 #define PCCR1_SGMIIA_KX_MASK            0x00008000
  54 #define PCCR1_SGMIIB_KX_MASK            0x00004000
  55 #define PCCR1_SGMIIC_KX_MASK            0x00002000
  56 #define PCCR1_SGMIID_KX_MASK            0x00001000
  57 #define PCCR1_SGMIIE_KX_MASK            0x00000800
  58 #define PCCR1_SGMIIF_KX_MASK            0x00000400
  59 #define PCCR1_SGMIIG_KX_MASK            0x00000200
  60 #define PCCR1_SGMIIH_KX_MASK            0x00000100
  61
  62 static int mdio_mux[NUM_FM_PORTS];
  63
  64 static const char * const mdio_names[] = {
  65 #if defined(CONFIG_TARGET_T2080QDS)
  66         "T2080QDS_MDIO_RGMII1",
  67         "T2080QDS_MDIO_RGMII2",
  68         "T2080QDS_MDIO_SLOT1",
  69         "T2080QDS_MDIO_SLOT3",
  70         "T2080QDS_MDIO_SLOT4",
  71         "T2080QDS_MDIO_SLOT5",
  72         "T2080QDS_MDIO_SLOT2",
  73         "T2080QDS_MDIO_10GC",
  74 #elif defined(CONFIG_TARGET_T2081QDS)
  75         "T2081QDS_MDIO_RGMII1",
  76         "T2081QDS_MDIO_RGMII2",
  77         "T2081QDS_MDIO_SLOT1",
  78         "T2081QDS_MDIO_SLOT2",
  79         "T2081QDS_MDIO_SLOT3",
  80         "T2081QDS_MDIO_SLOT5",
  81         "T2081QDS_MDIO_SLOT6",
  82         "T2081QDS_MDIO_SLOT7",
  83         "T2081QDS_MDIO_10GC",
  84 #endif
  85 };
  86
  87 /* Map SerDes1 8 lanes to default slot, will be initialized dynamically */
  88 #if defined(CONFIG_TARGET_T2080QDS)
  89 static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1};
  90 #elif defined(CONFIG_TARGET_T2081QDS)
  91 static u8 lane_to_slot[] = {2, 2, 2, 2, 1, 1, 1, 1};
  92 #endif
  93
  94 static const char *t208xqds_mdio_name_for_muxval(u8 muxval)
  95 {
  96         return mdio_names[muxval];
  97 }
  98
  99 struct mii_dev *mii_dev_for_muxval(u8 muxval)
 100 {
 101         struct mii_dev *bus;
 102         const char *name = t208xqds_mdio_name_for_muxval(muxval);
 103
 104         if (!name) {
 105                 printf("No bus for muxval %x\n", muxval);
 106                 return NULL;
 107         }
 108
 109         bus = miiphy_get_dev_by_name(name);
 110
 111         if (!bus) {
 112                 printf("No bus by name %s\n", name);
 113                 return NULL;
 114         }
 115
 116         return bus;
 117 }
 118
 119 struct t208xqds_mdio {
 120         u8 muxval;
 121         struct mii_dev *realbus;
 122 };
 123
 124 static void t208xqds_mux_mdio(u8 muxval)
 125 {
 126         u8 brdcfg4;
 127         if (muxval < 8) {
 128                 brdcfg4 = QIXIS_READ(brdcfg[4]);
 129                 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
 130                 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
 131                 QIXIS_WRITE(brdcfg[4], brdcfg4);
 132         }
 133 }
 134
 135 static int t208xqds_mdio_read(struct mii_dev *bus, int addr, int devad,
 136                                 int regnum)
 137 {
 138         struct t208xqds_mdio *priv = bus->priv;
 139
 140         t208xqds_mux_mdio(priv->muxval);
 141
 142         return priv->realbus->read(priv->realbus, addr, devad, regnum);
 143 }
 144
 145 static int t208xqds_mdio_write(struct mii_dev *bus, int addr, int devad,
 146                                 int regnum, u16 value)
 147 {
 148         struct t208xqds_mdio *priv = bus->priv;
 149
 150         t208xqds_mux_mdio(priv->muxval);
 151
 152         return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
 153 }
 154
 155 static int t208xqds_mdio_reset(struct mii_dev *bus)
 156 {
 157         struct t208xqds_mdio *priv = bus->priv;
 158
 159         return priv->realbus->reset(priv->realbus);
 160 }
 161
 162 static int t208xqds_mdio_init(char *realbusname, u8 muxval)
 163 {
 164         struct t208xqds_mdio *pmdio;
 165         struct mii_dev *bus = mdio_alloc();
 166
 167         if (!bus) {
 168                 printf("Failed to allocate t208xqds MDIO bus\n");
 169                 return -1;
 170         }
 171
 172         pmdio = malloc(sizeof(*pmdio));
 173         if (!pmdio) {
 174                 printf("Failed to allocate t208xqds private data\n");
 175                 free(bus);
 176                 return -1;
 177         }
 178
 179         bus->read = t208xqds_mdio_read;
 180         bus->write = t208xqds_mdio_write;
 181         bus->reset = t208xqds_mdio_reset;
 182         strcpy(bus->name, t208xqds_mdio_name_for_muxval(muxval));
 183
 184         pmdio->realbus = miiphy_get_dev_by_name(realbusname);
 185
 186         if (!pmdio->realbus) {
 187                 printf("No bus with name %s\n", realbusname);
 188                 free(bus);
 189                 free(pmdio);
 190                 return -1;
 191         }
 192
 193         pmdio->muxval = muxval;
 194         bus->priv = pmdio;
 195         return mdio_register(bus);
 196 }
 197
 198 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 199                                 enum fm_port port, int offset)
 200 {
 201         int phy;
 202         char alias[20];
 203         char lane_mode[2][20] = {"1000BASE-KX", "10GBASE-KR"};
 204         char buf[32] = "serdes-1,";
 205         struct fixed_link f_link;
 206         int media_type = 0;
 207         const char *phyconn;
 208         int off;
 209
 210         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 211 #ifdef CONFIG_TARGET_T2080QDS
 212         serdes_corenet_t *srds_regs =
 213                 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
 214         u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1);
 215 #endif
 216         u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
 217                                 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 218
 219         srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 220
 221         if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
 222                 phy = fm_info_get_phy_address(port);
 223                 switch (port) {
 224 #if defined(CONFIG_TARGET_T2080QDS)
 225                 case FM1_DTSEC1:
 226                         if (hwconfig_sub("fsl_1gkx", "fm1_1g1")) {
 227                                 media_type = 1;
 228                                 fdt_set_phy_handle(fdt, compat, addr,
 229                                                    "phy_1gkx1");
 230                                 fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio1");
 231                                 sprintf(buf, "%s%s%s", buf, "lane-c,",
 232                                                 (char *)lane_mode[0]);
 233                                 out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
 234                                          PCCR1_SGMIIH_KX_MASK);
 235                                 break;
 236                         }
 237                 case FM1_DTSEC2:
 238                         if (hwconfig_sub("fsl_1gkx", "fm1_1g2")) {
 239                                 media_type = 1;
 240                                 fdt_set_phy_handle(fdt, compat, addr,
 241                                                    "phy_1gkx2");
 242                                 fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio2");
 243                                 sprintf(buf, "%s%s%s", buf, "lane-d,",
 244                                                 (char *)lane_mode[0]);
 245                                 out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
 246                                          PCCR1_SGMIIG_KX_MASK);
 247                                 break;
 248                         }
 249                 case FM1_DTSEC9:
 250                         if (hwconfig_sub("fsl_1gkx", "fm1_1g9")) {
 251                                 media_type = 1;
 252                                 fdt_set_phy_handle(fdt, compat, addr,
 253                                                    "phy_1gkx9");
 254                                 fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio9");
 255                                 sprintf(buf, "%s%s%s", buf, "lane-a,",
 256                                                 (char *)lane_mode[0]);
 257                                 out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
 258                                          PCCR1_SGMIIE_KX_MASK);
 259                                 break;
 260                         }
 261                 case FM1_DTSEC10:
 262                         if (hwconfig_sub("fsl_1gkx", "fm1_1g10")) {
 263                                 media_type = 1;
 264                                 fdt_set_phy_handle(fdt, compat, addr,
 265                                                    "phy_1gkx10");
 266                                 fdt_status_okay_by_alias(fdt,
 267                                                          "1gkx_pcs_mdio10");
 268                                 sprintf(buf, "%s%s%s", buf, "lane-b,",
 269                                                 (char *)lane_mode[0]);
 270                                 out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
 271                                          PCCR1_SGMIIF_KX_MASK);
 272                                 break;
 273                         }
 274                         if (mdio_mux[port] == EMI1_SLOT2) {
 275                                 sprintf(alias, "phy_sgmii_s2_%x", phy);
 276                                 fdt_set_phy_handle(fdt, compat, addr, alias);
 277                                 fdt_status_okay_by_alias(fdt, "emi1_slot2");
 278                         } else if (mdio_mux[port] == EMI1_SLOT3) {
 279                                 sprintf(alias, "phy_sgmii_s3_%x", phy);
 280                                 fdt_set_phy_handle(fdt, compat, addr, alias);
 281                                 fdt_status_okay_by_alias(fdt, "emi1_slot3");
 282                         }
 283                         break;
 284                 case FM1_DTSEC5:
 285                         if (hwconfig_sub("fsl_1gkx", "fm1_1g5")) {
 286                                 media_type = 1;
 287                                 fdt_set_phy_handle(fdt, compat, addr,
 288                                                    "phy_1gkx5");
 289                                 fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio5");
 290                                 sprintf(buf, "%s%s%s", buf, "lane-g,",
 291                                                 (char *)lane_mode[0]);
 292                                 out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
 293                                          PCCR1_SGMIIC_KX_MASK);
 294                                 break;
 295                         }
 296                 case FM1_DTSEC6:
 297                         if (hwconfig_sub("fsl_1gkx", "fm1_1g6")) {
 298                                 media_type = 1;
 299                                 fdt_set_phy_handle(fdt, compat, addr,
 300                                                    "phy_1gkx6");
 301                                 fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio6");
 302                                 sprintf(buf, "%s%s%s", buf, "lane-h,",
 303                                                 (char *)lane_mode[0]);
 304                                 out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
 305                                          PCCR1_SGMIID_KX_MASK);
 306                                 break;
 307                         }
 308                         if (mdio_mux[port] == EMI1_SLOT1) {
 309                                 sprintf(alias, "phy_sgmii_s1_%x", phy);
 310                                 fdt_set_phy_handle(fdt, compat, addr, alias);
 311                                 fdt_status_okay_by_alias(fdt, "emi1_slot1");
 312                         } else if (mdio_mux[port] == EMI1_SLOT2) {
 313                                 sprintf(alias, "phy_sgmii_s2_%x", phy);
 314                                 fdt_set_phy_handle(fdt, compat, addr, alias);
 315                                 fdt_status_okay_by_alias(fdt, "emi1_slot2");
 316                         }
 317                         break;
 318 #elif defined(CONFIG_TARGET_T2081QDS)
 319                 case FM1_DTSEC1:
 320                 case FM1_DTSEC2:
 321                 case FM1_DTSEC5:
 322                 case FM1_DTSEC6:
 323                 case FM1_DTSEC9:
 324                 case FM1_DTSEC10:
 325                         if (mdio_mux[port] == EMI1_SLOT2) {
 326                                 sprintf(alias, "phy_sgmii_s2_%x", phy);
 327                                 fdt_set_phy_handle(fdt, compat, addr, alias);
 328                                 fdt_status_okay_by_alias(fdt, "emi1_slot2");
 329                         } else if (mdio_mux[port] == EMI1_SLOT3) {
 330                                 sprintf(alias, "phy_sgmii_s3_%x", phy);
 331                                 fdt_set_phy_handle(fdt, compat, addr, alias);
 332                                 fdt_status_okay_by_alias(fdt, "emi1_slot3");
 333                         } else if (mdio_mux[port] == EMI1_SLOT5) {
 334                                 sprintf(alias, "phy_sgmii_s5_%x", phy);
 335                                 fdt_set_phy_handle(fdt, compat, addr, alias);
 336                                 fdt_status_okay_by_alias(fdt, "emi1_slot5");
 337                         } else if (mdio_mux[port] == EMI1_SLOT6) {
 338                                 sprintf(alias, "phy_sgmii_s6_%x", phy);
 339                                 fdt_set_phy_handle(fdt, compat, addr, alias);
 340                                 fdt_status_okay_by_alias(fdt, "emi1_slot6");
 341                         } else if (mdio_mux[port] == EMI1_SLOT7) {
 342                                 sprintf(alias, "phy_sgmii_s7_%x", phy);
 343                                 fdt_set_phy_handle(fdt, compat, addr, alias);
 344                                 fdt_status_okay_by_alias(fdt, "emi1_slot7");
 345                         }
 346                         break;
 347 #endif
 348                 default:
 349                         break;
 350                 }
 351                 if (media_type) {
 352                         /* set property for 1000BASE-KX in dtb */
 353                         off = fdt_node_offset_by_compat_reg(fdt,
 354                                         "fsl,fman-memac-mdio", addr + 0x1000);
 355                         fdt_setprop_string(fdt, off, "lane-instance", buf);
 356                 }
 357
 358         } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
 359                 switch (srds_s1) {
 360                 case 0x66: /* XFI interface */
 361                 case 0x6b:
 362                 case 0x6c:
 363                 case 0x6d:
 364                 case 0x71:
 365                         /*
 366                         * if the 10G is XFI, check hwconfig to see what is the
 367                         * media type, there are two types, fiber or copper,
 368                         * fix the dtb accordingly.
 369                         */
 370                         switch (port) {
 371                         case FM1_10GEC1:
 372                         if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
 373                                 /* it's MAC9 */
 374                                 media_type = 1;
 375                                 fdt_set_phy_handle(fdt, compat, addr,
 376                                                 "phy_xfi9");
 377                                 fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio9");
 378                                 sprintf(buf, "%s%s%s", buf, "lane-a,",
 379                                                 (char *)lane_mode[1]);
 380                         }
 381                                 break;
 382                         case FM1_10GEC2:
 383                         if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) {
 384                                 /* it's MAC10 */
 385                                 media_type = 1;
 386                                 fdt_set_phy_handle(fdt, compat, addr,
 387                                                 "phy_xfi10");
 388                                 fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio10");
 389                                 sprintf(buf, "%s%s%s", buf, "lane-b,",
 390                                                 (char *)lane_mode[1]);
 391                         }
 392                                 break;
 393                         case FM1_10GEC3:
 394                         if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g3")) {
 395                                 /* it's MAC1 */
 396                                 media_type = 1;
 397                                 fdt_set_phy_handle(fdt, compat, addr,
 398                                                 "phy_xfi1");
 399                                 fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio1");
 400                                 sprintf(buf, "%s%s%s", buf, "lane-c,",
 401                                                 (char *)lane_mode[1]);
 402                         }
 403                                 break;
 404                         case FM1_10GEC4:
 405                         if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g4")) {
 406                                 /* it's MAC2 */
 407                                 media_type = 1;
 408                                 fdt_set_phy_handle(fdt, compat, addr,
 409                                                 "phy_xfi2");
 410                                 fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio2");
 411                                 sprintf(buf, "%s%s%s", buf, "lane-d,",
 412                                                 (char *)lane_mode[1]);
 413                         }
 414                                 break;
 415                         default:
 416                                 return;
 417                         }
 418
 419                         if (!media_type) {
 420                                 phyconn = fdt_getprop(fdt, offset,
 421                                                       "phy-connection-type",
 422                                                       NULL);
 423                                 if (is_backplane_mode(phyconn)) {
 424                                         /* Backplane KR mode: skip fixups */
 425                                         printf("Interface %d in backplane KR mode\n",
 426                                                port);
 427                                 } else {
 428                                         /* fixed-link for XFI fiber cable */
 429                                         f_link.phy_id = port;
 430                                         f_link.duplex = 1;
 431                                         f_link.link_speed = 10000;
 432                                         f_link.pause = 0;
 433                                         f_link.asym_pause = 0;
 434                                         fdt_delprop(fdt, offset, "phy-handle");
 435                                         fdt_setprop(fdt, offset, "fixed-link",
 436                                                     &f_link, sizeof(f_link));
 437                                 }
 438                         } else {
 439                                 /* set property for copper cable */
 440                                 off = fdt_node_offset_by_compat_reg(fdt,
 441                                         "fsl,fman-memac-mdio", addr + 0x1000);
 442                                 fdt_setprop_string(fdt, off,
 443                                         "lane-instance", buf);
 444                         }
 445                         break;
 446                 default:
 447                         break;
 448                 }
 449         }
 450 }
 451
 452 void fdt_fixup_board_enet(void *fdt)
 453 {
 454         return;
 455 }
 456
 457 /*
 458  * This function reads RCW to check if Serdes1{A:H} is configured
 459  * to slot 1/2/3/4/5/6/7 and update the lane_to_slot[] array accordingly
 460  */
 461 static void initialize_lane_to_slot(void)
 462 {
 463         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 464         u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
 465                                 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 466
 467         srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 468
 469         switch (srds_s1) {
 470 #if defined(CONFIG_TARGET_T2080QDS)
 471         case 0x51:
 472         case 0x5f:
 473         case 0x65:
 474         case 0x6b:
 475         case 0x71:
 476                 lane_to_slot[5] = 2;
 477                 lane_to_slot[6] = 2;
 478                 lane_to_slot[7] = 2;
 479                 break;
 480         case 0xa6:
 481         case 0x8e:
 482         case 0x8f:
 483         case 0x82:
 484         case 0x83:
 485         case 0xd3:
 486         case 0xd9:
 487         case 0xcb:
 488                 lane_to_slot[6] = 2;
 489                 lane_to_slot[7] = 2;
 490                 break;
 491         case 0xda:
 492                 lane_to_slot[4] = 3;
 493                 lane_to_slot[5] = 3;
 494                 lane_to_slot[6] = 3;
 495                 lane_to_slot[7] = 3;
 496                 break;
 497 #elif defined(CONFIG_TARGET_T2081QDS)
 498         case 0x6b:
 499                 lane_to_slot[4] = 1;
 500                 lane_to_slot[5] = 3;
 501                 lane_to_slot[6] = 3;
 502                 lane_to_slot[7] = 3;
 503                 break;
 504         case 0xca:
 505         case 0xcb:
 506                 lane_to_slot[1] = 7;
 507                 lane_to_slot[2] = 6;
 508                 lane_to_slot[3] = 5;
 509                 lane_to_slot[5] = 3;
 510                 lane_to_slot[6] = 3;
 511                 lane_to_slot[7] = 3;
 512                 break;
 513         case 0xf2:
 514                 lane_to_slot[1] = 7;
 515                 lane_to_slot[2] = 7;
 516                 lane_to_slot[3] = 7;
 517                 lane_to_slot[5] = 4;
 518                 lane_to_slot[6] = 3;
 519                 lane_to_slot[7] = 7;
 520                 break;
 521 #endif
 522         default:
 523                 break;
 524         }
 525 }
 526
 527 int board_eth_init(bd_t *bis)
 528 {
 529 #if defined(CONFIG_FMAN_ENET)
 530         int i, idx, lane, slot, interface;
 531         struct memac_mdio_info dtsec_mdio_info;
 532         struct memac_mdio_info tgec_mdio_info;
 533         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 534         u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
 535         u32 srds_s1;
 536
 537         srds_s1 = in_be32(&gur->rcwsr[4]) &
 538                                         FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 539         srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 540
 541         initialize_lane_to_slot();
 542
 543         /* Initialize the mdio_mux array so we can recognize empty elements */
 544         for (i = 0; i < NUM_FM_PORTS; i++)
 545                 mdio_mux[i] = EMI_NONE;
 546
 547         dtsec_mdio_info.regs =
 548                 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
 549
 550         dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 551
 552         /* Register the 1G MDIO bus */
 553         fm_memac_mdio_init(bis, &dtsec_mdio_info);
 554
 555         tgec_mdio_info.regs =
 556                 (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
 557         tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
 558
 559         /* Register the 10G MDIO bus */
 560         fm_memac_mdio_init(bis, &tgec_mdio_info);
 561
 562         /* Register the muxing front-ends to the MDIO buses */
 563         t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
 564         t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
 565         t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
 566         t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
 567         t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
 568 #if defined(CONFIG_TARGET_T2080QDS)
 569         t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
 570 #endif
 571         t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
 572 #if defined(CONFIG_TARGET_T2081QDS)
 573         t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
 574         t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
 575 #endif
 576         t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
 577
 578         /* Set the two on-board RGMII PHY address */
 579         fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
 580         if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
 581                         FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII)
 582                 fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
 583         else
 584                 fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR);
 585
 586         switch (srds_s1) {
 587         case 0x1b:
 588         case 0x1c:
 589         case 0x95:
 590         case 0xa2:
 591         case 0x94:
 592                 /* T2080QDS: SGMII in Slot3;  T2081QDS: SGMII in Slot2 */
 593                 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
 594                 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
 595                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
 596                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
 597                 /* T2080QDS: SGMII in Slot2;  T2081QDS: SGMII in Slot1 */
 598                 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
 599                 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
 600                 break;
 601         case 0x50:
 602         case 0x51:
 603         case 0x5e:
 604         case 0x5f:
 605         case 0x64:
 606         case 0x65:
 607                 /* T2080QDS: XAUI/HiGig in Slot3;  T2081QDS: in Slot2 */
 608                 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
 609                 /* T2080QDS: SGMII in Slot2;  T2081QDS: in Slot3 */
 610                 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
 611                 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
 612                 break;
 613         case 0x66:
 614         case 0x67:
 615                 /*
 616                  * XFI does not need a PHY to work, but to avoid U-Boot use
 617                  * default PHY address which is zero to a MAC when it found
 618                  * a MAC has no PHY address, we give a PHY address to XFI
 619                  * MAC, and should not use a real XAUI PHY address, since
 620                  * MDIO can access it successfully, and then MDIO thinks
 621                  * the XAUI card is used for the XFI MAC, which will cause
 622                  * error.
 623                  */
 624                 fm_info_set_phy_address(FM1_10GEC1, 4);
 625                 fm_info_set_phy_address(FM1_10GEC2, 5);
 626                 fm_info_set_phy_address(FM1_10GEC3, 6);
 627                 fm_info_set_phy_address(FM1_10GEC4, 7);
 628                 break;
 629         case 0x6a:
 630         case 0x6b:
 631                 fm_info_set_phy_address(FM1_10GEC1, 4);
 632                 fm_info_set_phy_address(FM1_10GEC2, 5);
 633                 fm_info_set_phy_address(FM1_10GEC3, 6);
 634                 fm_info_set_phy_address(FM1_10GEC4, 7);
 635                 /* T2080QDS: SGMII in Slot2;  T2081QDS: in Slot3 */
 636                 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
 637                 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
 638                 break;
 639         case 0x6c:
 640         case 0x6d:
 641                 fm_info_set_phy_address(FM1_10GEC1, 4);
 642                 fm_info_set_phy_address(FM1_10GEC2, 5);
 643                 /* T2080QDS: SGMII in Slot3;  T2081QDS: in Slot2 */
 644                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
 645                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
 646                 break;
 647         case 0x70:
 648         case 0x71:
 649                 /* SGMII in Slot3 */
 650                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
 651                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
 652                 /* SGMII in Slot2 */
 653                 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
 654                 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
 655                 break;
 656         case 0xa6:
 657         case 0x8e:
 658         case 0x8f:
 659         case 0x82:
 660         case 0x83:
 661                 /* SGMII in Slot3 */
 662                 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
 663                 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
 664                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
 665                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
 666                 /* SGMII in Slot2 */
 667                 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
 668                 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
 669                 break;
 670         case 0xa4:
 671         case 0x96:
 672         case 0x8a:
 673                 /* SGMII in Slot3 */
 674                 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
 675                 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
 676                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
 677                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
 678                 break;
 679 #if defined(CONFIG_TARGET_T2080QDS)
 680         case 0xd9:
 681         case 0xd3:
 682         case 0xcb:
 683                 /* SGMII in Slot3 */
 684                 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
 685                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
 686                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
 687                 /* SGMII in Slot2 */
 688                 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
 689                 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
 690                 break;
 691 #elif defined(CONFIG_TARGET_T2081QDS)
 692         case 0xca:
 693         case 0xcb:
 694                 /* SGMII in Slot3 */
 695                 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
 696                 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
 697                 /* SGMII in Slot5 */
 698                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
 699                 /* SGMII in Slot6 */
 700                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
 701                 /* SGMII in Slot7 */
 702                 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
 703                 break;
 704 #endif
 705         case 0xf2:
 706                 /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */
 707                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
 708                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
 709                 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
 710                 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
 711                 break;
 712         default:
 713                 break;
 714         }
 715
 716         for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
 717                 idx = i - FM1_DTSEC1;
 718                 interface = fm_info_get_enet_if(i);
 719                 switch (interface) {
 720                 case PHY_INTERFACE_MODE_SGMII:
 721                         lane = serdes_get_first_lane(FSL_SRDS_1,
 722                                         SGMII_FM1_DTSEC1 + idx);
 723                         if (lane < 0)
 724                                 break;
 725                         slot = lane_to_slot[lane];
 726                         debug("FM1@DTSEC%u expects SGMII in slot %u\n",
 727                               idx + 1, slot);
 728                         if (QIXIS_READ(present2) & (1 << (slot - 1)))
 729                                 fm_disable_port(i);
 730
 731                         switch (slot) {
 732                         case 1:
 733                                 mdio_mux[i] = EMI1_SLOT1;
 734                                 fm_info_set_mdio(i, mii_dev_for_muxval(
 735                                                  mdio_mux[i]));
 736                                 break;
 737                         case 2:
 738                                 mdio_mux[i] = EMI1_SLOT2;
 739                                 fm_info_set_mdio(i, mii_dev_for_muxval(
 740                                                  mdio_mux[i]));
 741                                 break;
 742                         case 3:
 743                                 mdio_mux[i] = EMI1_SLOT3;
 744                                 fm_info_set_mdio(i, mii_dev_for_muxval(
 745                                                  mdio_mux[i]));
 746                                 break;
 747 #if defined(CONFIG_TARGET_T2081QDS)
 748                         case 5:
 749                                 mdio_mux[i] = EMI1_SLOT5;
 750                                 fm_info_set_mdio(i, mii_dev_for_muxval(
 751                                                  mdio_mux[i]));
 752                                 break;
 753                         case 6:
 754                                 mdio_mux[i] = EMI1_SLOT6;
 755                                 fm_info_set_mdio(i, mii_dev_for_muxval(
 756                                                  mdio_mux[i]));
 757                                 break;
 758                         case 7:
 759                                 mdio_mux[i] = EMI1_SLOT7;
 760                                 fm_info_set_mdio(i, mii_dev_for_muxval(
 761                                                  mdio_mux[i]));
 762                                 break;
 763 #endif
 764                         }
 765                         break;
 766                 case PHY_INTERFACE_MODE_RGMII:
 767                         if (i == FM1_DTSEC3)
 768                                 mdio_mux[i] = EMI1_RGMII1;
 769                         else if (i == FM1_DTSEC4 || FM1_DTSEC10)
 770                                 mdio_mux[i] = EMI1_RGMII2;
 771                         fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 772                         break;
 773                 default:
 774                         break;
 775                 }
 776         }
 777
 778         for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
 779                 idx = i - FM1_10GEC1;
 780                 switch (fm_info_get_enet_if(i)) {
 781                 case PHY_INTERFACE_MODE_XGMII:
 782                         if (srds_s1 == 0x51) {
 783                                 lane = serdes_get_first_lane(FSL_SRDS_1,
 784                                                 XAUI_FM1_MAC9 + idx);
 785                         } else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) {
 786                                 lane = serdes_get_first_lane(FSL_SRDS_1,
 787                                                 HIGIG_FM1_MAC9 + idx);
 788                         } else {
 789                                 if (i == FM1_10GEC1 || i == FM1_10GEC2)
 790                                         lane = serdes_get_first_lane(FSL_SRDS_1,
 791                                                 XFI_FM1_MAC9 + idx);
 792                                 else
 793                                         lane = serdes_get_first_lane(FSL_SRDS_1,
 794                                                 XFI_FM1_MAC1 + idx);
 795                         }
 796
 797                         if (lane < 0)
 798                                 break;
 799                         mdio_mux[i] = EMI2;
 800                         fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 801
 802                         if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) ||
 803                             (srds_s1 == 0x6a) || (srds_s1 == 0x70) ||
 804                             (srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||
 805                             (srds_s1 == 0x71)) {
 806                                 /* As XFI is in cage intead of a slot, so
 807                                  * ensure doesn't disable the corresponding port
 808                                  */
 809                                 break;
 810                         }
 811
 812                         slot = lane_to_slot[lane];
 813                         if (QIXIS_READ(present2) & (1 << (slot - 1)))
 814                                 fm_disable_port(i);
 815                         break;
 816                 default:
 817                         break;
 818                 }
 819         }
 820
 821         cpu_eth_init(bis);
 822 #endif /* CONFIG_FMAN_ENET */
 823
 824         return pci_eth_init(bis);
 825 }