1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright 2013 Freescale Semiconductor, Inc.
6 #include <clock_legacy.h>
8 #include <env_internal.h>
15 #include <fsl_esdhc.h>
16 #include <spi_flash.h>
17 #include "../common/sleep.h"
18 #include "../common/spl.h"
20 DECLARE_GLOBAL_DATA_PTR;
22 phys_size_t get_effective_memsize(void)
24 return CONFIG_SYS_L3_SIZE;
27 unsigned long get_board_sys_clk(void)
29 return CONFIG_SYS_CLK_FREQ;
32 unsigned long get_board_ddr_clk(void)
34 return CONFIG_DDR_CLK_FREQ;
37 #define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
38 void board_init_f(ulong bootflag)
40 u32 plat_ratio, sys_clk, uart_clk;
41 #if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
45 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
47 #if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
48 if (IS_SVR_REV(svr, 1, 0)) {
50 * There is T1040 SoC issue where NOR, FPGA are inaccessible
51 * during NAND boot because IFC signals > IFC_AD7 are not
52 * enabled. This workaround changes RCW source to make all
55 porsr1 = in_be32(&gur->porsr1);
56 pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK))
58 out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000),
63 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
64 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
66 /* Update GD pointer */
67 gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
69 #ifdef CONFIG_DEEP_SLEEP
70 /* disable the console if boot from deep sleep */
72 fsl_dp_disable_console();
74 /* compiler optimization barrier needed for GCC >= 3.4 */
75 __asm__ __volatile__("" : : : "memory");
79 /* initialize selected port with appropriate baud rate */
80 sys_clk = get_board_sys_clk();
81 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
82 uart_clk = sys_clk * plat_ratio / 2;
84 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
85 uart_clk / 16 / CONFIG_BAUDRATE);
87 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
90 void board_init_r(gd_t *gd, ulong dest_addr)
94 bd = (struct bd_info *)(gd + sizeof(gd_t));
95 memset(bd, 0, sizeof(struct bd_info));
97 bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
98 bd->bi_memsize = CONFIG_SYS_L3_SIZE;
102 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
103 CONFIG_SPL_RELOC_MALLOC_SIZE);
104 gd->flags |= GD_FLG_FULL_MALLOC_INIT;
106 #ifdef CONFIG_SPL_MMC_BOOT
110 /* relocate environment function pointers etc. */
111 #if defined(CONFIG_ENV_IS_IN_NAND) || defined(CONFIG_ENV_IS_IN_MMC) || \
112 defined(CONFIG_ENV_IS_IN_SPI_FLASH)
113 #ifdef CONFIG_SPL_NAND_BOOT
114 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
115 (uchar *)SPL_ENV_ADDR);
117 #ifdef CONFIG_SPL_MMC_BOOT
118 mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
119 (uchar *)SPL_ENV_ADDR);
121 #ifdef CONFIG_SPL_SPI_BOOT
122 fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
123 (uchar *)SPL_ENV_ADDR);
125 gd->env_addr = (ulong)(SPL_ENV_ADDR);
126 gd->env_valid = ENV_VALID;
135 #ifdef CONFIG_SPL_MMC_BOOT
137 #elif defined(CONFIG_SPL_SPI_BOOT)
139 #elif defined(CONFIG_SPL_NAND_BOOT)