board/freescale/t104xrdb/eth.c

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <netdev.h>
   9 #include <asm/fsl_serdes.h>
  10 #include <asm/immap_85xx.h>
  11 #include <fm_eth.h>
  12 #include <fsl_mdio.h>
  13 #include <malloc.h>
  14 #include <fsl_dtsec.h>
  15 #include <vsc9953.h>
  16
  17 #include "../common/fman.h"
  18
  19 int board_eth_init(bd_t *bis)
  20 {
  21 #ifdef CONFIG_FMAN_ENET
  22         struct memac_mdio_info memac_mdio_info;
  23         unsigned int i;
  24         int phy_addr = 0;
  25 #ifdef CONFIG_VSC9953
  26         phy_interface_t phy_int;
  27         struct mii_dev *bus;
  28 #endif
  29
  30         printf("Initializing Fman\n");
  31
  32         memac_mdio_info.regs =
  33                 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
  34         memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  35
  36         /* Register the real 1G MDIO bus */
  37         fm_memac_mdio_init(bis, &memac_mdio_info);
  38
  39         /*
  40          * Program on board RGMII, SGMII PHY addresses.
  41          */
  42         for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  43                 int idx = i - FM1_DTSEC1;
  44
  45                 switch (fm_info_get_enet_if(i)) {
  46 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
  47                 case PHY_INTERFACE_MODE_SGMII:
  48                         /* T1040RDB & T1040D4RDB only supports SGMII on
  49                          * DTSEC3
  50                          */
  51                         fm_info_set_phy_address(FM1_DTSEC3,
  52                                                 CONFIG_SYS_SGMII1_PHY_ADDR);
  53                         break;
  54 #endif
  55 #ifdef CONFIG_TARGET_T1042RDB
  56                 case PHY_INTERFACE_MODE_SGMII:
  57                         /* T1042RDB doesn't supports SGMII on DTSEC1 & DTSEC2 */
  58                         if ((FM1_DTSEC1 == i) || (FM1_DTSEC2 == i))
  59                                 fm_info_set_phy_address(i, 0);
  60                         /* T1042RDB only supports SGMII on DTSEC3 */
  61                         fm_info_set_phy_address(FM1_DTSEC3,
  62                                                 CONFIG_SYS_SGMII1_PHY_ADDR);
  63                         break;
  64 #endif
  65 #ifdef CONFIG_TARGET_T1042D4RDB
  66                 case PHY_INTERFACE_MODE_SGMII:
  67                         /* T1042D4RDB supports SGMII on DTSEC1, DTSEC2
  68                          *  & DTSEC3
  69                          */
  70                         if (FM1_DTSEC1 == i)
  71                                 phy_addr = CONFIG_SYS_SGMII1_PHY_ADDR;
  72                         if (FM1_DTSEC2 == i)
  73                                 phy_addr = CONFIG_SYS_SGMII2_PHY_ADDR;
  74                         if (FM1_DTSEC3 == i)
  75                                 phy_addr = CONFIG_SYS_SGMII3_PHY_ADDR;
  76                         fm_info_set_phy_address(i, phy_addr);
  77                         break;
  78 #endif
  79                 case PHY_INTERFACE_MODE_RGMII:
  80                         if (FM1_DTSEC4 == i)
  81                                 phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR;
  82                         if (FM1_DTSEC5 == i)
  83                                 phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR;
  84                         fm_info_set_phy_address(i, phy_addr);
  85                         break;
  86                 case PHY_INTERFACE_MODE_QSGMII:
  87                         fm_info_set_phy_address(i, 0);
  88                         break;
  89                 case PHY_INTERFACE_MODE_NONE:
  90                         fm_info_set_phy_address(i, 0);
  91                         break;
  92                 default:
  93                         printf("Fman1: DTSEC%u set to unknown interface %i\n",
  94                                idx + 1, fm_info_get_enet_if(i));
  95                         fm_info_set_phy_address(i, 0);
  96                         break;
  97                 }
  98                 if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_QSGMII ||
  99                     fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_NONE)
 100                         fm_info_set_mdio(i, NULL);
 101                 else
 102                         fm_info_set_mdio(i,
 103                                          miiphy_get_dev_by_name(
 104                                                         DEFAULT_FM_MDIO_NAME));
 105         }
 106
 107 #ifdef CONFIG_VSC9953
 108         /* SerDes configured for QSGMII */
 109         if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A) >= 0) {
 110                 for (i = 0; i < 4; i++) {
 111                         bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
 112                         phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR + i;
 113                         phy_int = PHY_INTERFACE_MODE_QSGMII;
 114
 115                         vsc9953_port_info_set_mdio(i, bus);
 116                         vsc9953_port_info_set_phy_address(i, phy_addr);
 117                         vsc9953_port_info_set_phy_int(i, phy_int);
 118                         vsc9953_port_enable(i);
 119                 }
 120         }
 121         if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B) >= 0) {
 122                 for (i = 4; i < 8; i++) {
 123                         bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
 124                         phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR + i - 4;
 125                         phy_int = PHY_INTERFACE_MODE_QSGMII;
 126
 127                         vsc9953_port_info_set_mdio(i, bus);
 128                         vsc9953_port_info_set_phy_address(i, phy_addr);
 129                         vsc9953_port_info_set_phy_int(i, phy_int);
 130                         vsc9953_port_enable(i);
 131                 }
 132         }
 133
 134         /* Connect DTSEC1 to L2 switch if it doesn't have a PHY */
 135         if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1) < 0)
 136                 vsc9953_port_enable(8);
 137
 138         /* Connect DTSEC2 to L2 switch if it doesn't have a PHY */
 139         if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC2) < 0) {
 140                 /* Enable L2 On MAC2 using SCFG */
 141                 struct ccsr_scfg *scfg = (struct ccsr_scfg *)
 142                                 CONFIG_SYS_MPC85xx_SCFG;
 143
 144                 out_be32(&scfg->esgmiiselcr, in_be32(&scfg->esgmiiselcr) |
 145                          (0x80000000));
 146                 vsc9953_port_enable(9);
 147         }
 148 #endif
 149
 150         cpu_eth_init(bis);
 151 #endif
 152
 153         return pci_eth_init(bis);
 154 }