1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2013 Freescale Semiconductor, Inc.
11 #include <linux/compiler.h>
13 #include <asm/processor.h>
14 #include <asm/cache.h>
15 #include <asm/immap_85xx.h>
16 #include <asm/fsl_law.h>
17 #include <asm/fsl_serdes.h>
18 #include <asm/fsl_liodn.h>
22 #include "../common/sleep.h"
23 #include "../common/qixis.h"
25 #include "t1040qds_qixis.h"
27 DECLARE_GLOBAL_DATA_PTR;
33 struct cpu_type *cpu = gd->arch.cpu;
34 static const char *const freq[] = {"100", "125", "156.25", "161.13",
35 "122.88", "122.88", "122.88"};
38 printf("Board: %sQDS, ", cpu->name);
39 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
40 QIXIS_READ(id), QIXIS_READ(arch));
42 sw = QIXIS_READ(brdcfg[0]);
43 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
46 printf("vBank: %d\n", sw);
54 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
56 printf("FPGA: v%d (%s), build %d",
57 (int)QIXIS_READ(scver), qixis_read_tag(buf),
58 (int)qixis_read_minor());
59 /* the timestamp string contains "\n" at the end */
60 printf(" on %s", qixis_read_time(buf));
63 * Display the actual SERDES reference clocks as configured by the
64 * dip switches on the board. Note that the SWx registers could
65 * technically be set to force the reference clocks to match the
66 * values that the SERDES expects (or vice versa). For now, however,
67 * we just display both values and hope the user notices when they
70 puts("SERDES Reference: ");
71 sw = QIXIS_READ(brdcfg[2]);
72 clock = (sw >> 6) & 3;
73 printf("Clock1=%sMHz ", freq[clock]);
74 clock = (sw >> 4) & 3;
75 printf("Clock2=%sMHz\n", freq[clock]);
80 int select_i2c_ch_pca9547(u8 ch)
84 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
86 puts("PCA: failed to select proper channel\n");
93 static void qe_board_setup(void)
97 if (hwconfig("qe") && hwconfig("tdm")) {
98 brdcfg15 = QIXIS_READ(brdcfg[15]);
100 * TDMRiser uses QE-TDM
101 * Route QE_TDM signals to TDM Riser slot
103 QIXIS_WRITE(brdcfg[15], brdcfg15 | 7);
104 } else if (hwconfig("qe") && hwconfig("uart")) {
105 brdcfg15 = QIXIS_READ(brdcfg[15]);
106 brdcfg9 = QIXIS_READ(brdcfg[9]);
108 * Route QE_TDM signals to UCC
109 * ProfiBus controlled by UCC3
112 QIXIS_WRITE(brdcfg[15], brdcfg15 | 2);
113 QIXIS_WRITE(brdcfg[9], brdcfg9 | 4);
117 int board_early_init_f(void)
119 #if defined(CONFIG_DEEP_SLEEP)
121 fsl_dp_disable_console();
127 int board_early_init_r(void)
129 #ifdef CONFIG_SYS_FLASH_BASE
130 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
131 int flash_esel = find_tlb_idx((void *)flashbase, 1);
134 * Remap Boot flash + PROMJET region to caching-inhibited
135 * so that flash can be erased properly.
138 /* Flush d-cache and invalidate i-cache of any FLASH data */
142 if (flash_esel == -1) {
143 /* very unlikely unless something is messed up */
144 puts("Error: Could not find TLB for FLASH BASE\n");
145 flash_esel = 2; /* give our best effort to continue */
147 /* invalidate existing TLB entry for flash + promjet */
148 disable_tlb(flash_esel);
151 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
152 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
153 0, flash_esel, BOOKE_PAGESZ_256M, 1);
155 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
160 unsigned long get_board_sys_clk(void)
162 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
164 switch (sysclk_conf & 0x0F) {
165 case QIXIS_SYSCLK_64:
167 case QIXIS_SYSCLK_83:
169 case QIXIS_SYSCLK_100:
171 case QIXIS_SYSCLK_125:
173 case QIXIS_SYSCLK_133:
175 case QIXIS_SYSCLK_150:
177 case QIXIS_SYSCLK_160:
179 case QIXIS_SYSCLK_166:
185 unsigned long get_board_ddr_clk(void)
187 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
189 switch ((ddrclk_conf & 0x30) >> 4) {
190 case QIXIS_DDRCLK_100:
192 case QIXIS_DDRCLK_125:
194 case QIXIS_DDRCLK_133:
200 #define NUM_SRDS_BANKS 2
201 int misc_init_r(void)
204 serdes_corenet_t *srds_regs =
205 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
206 u32 actual[NUM_SRDS_BANKS] = { 0 };
209 sw = QIXIS_READ(brdcfg[2]);
210 for (i = 0; i < NUM_SRDS_BANKS; i++) {
211 unsigned int clock = (sw >> (6 - 2 * i)) & 3;
214 actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
217 actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
220 actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
226 for (i = 0; i < NUM_SRDS_BANKS; i++) {
227 u32 pllcr0 = srds_regs->bank[i].pllcr0;
228 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
229 if (expected != actual[i]) {
230 printf("expects ref clk%d %sMHz, but actual is %sMHz\n",
231 i + 1, serdes_clock_to_string(expected),
232 serdes_clock_to_string(actual[i]));
241 int ft_board_setup(void *blob, bd_t *bd)
246 ft_cpu_setup(blob, bd);
248 base = env_get_bootm_low();
249 size = env_get_bootm_size();
251 fdt_fixup_memory(blob, (u64)base, (u64)size);
254 pci_of_setup(blob, bd);
257 fdt_fixup_liodn(blob);
259 #ifdef CONFIG_HAS_FSL_DR_USB
260 fsl_fdt_fixup_dr_usb(blob, bd);
263 #ifdef CONFIG_SYS_DPAA_FMAN
264 fdt_fixup_fman_ethernet(blob);
265 fdt_fixup_board_enet(blob);
271 void qixis_dump_switch(void)
275 QIXIS_WRITE(cms[0], 0x00);
276 nr_of_cfgsw = QIXIS_READ(cms[1]);
278 puts("DIP switch settings dump:\n");
279 for (i = 1; i <= nr_of_cfgsw; i++) {
280 QIXIS_WRITE(cms[0], i);
281 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
285 int board_need_mem_reset(void)