2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/compiler.h>
13 #include <asm/processor.h>
14 #include <asm/cache.h>
15 #include <asm/immap_85xx.h>
16 #include <asm/fsl_law.h>
17 #include <asm/fsl_serdes.h>
18 #include <asm/fsl_portals.h>
19 #include <asm/fsl_liodn.h>
21 #include <asm/mpc85xx_gpio.h>
23 #include "../common/qixis.h"
25 #include "t1040qds_qixis.h"
27 DECLARE_GLOBAL_DATA_PTR;
33 struct cpu_type *cpu = gd->arch.cpu;
34 static const char *const freq[] = {"100", "125", "156.25", "161.13",
35 "122.88", "122.88", "122.88"};
38 printf("Board: %sQDS, ", cpu->name);
39 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
40 QIXIS_READ(id), QIXIS_READ(arch));
42 sw = QIXIS_READ(brdcfg[0]);
43 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
46 printf("vBank: %d\n", sw);
54 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
56 printf("FPGA: v%d (%s), build %d",
57 (int)QIXIS_READ(scver), qixis_read_tag(buf),
58 (int)qixis_read_minor());
59 /* the timestamp string contains "\n" at the end */
60 printf(" on %s", qixis_read_time(buf));
63 * Display the actual SERDES reference clocks as configured by the
64 * dip switches on the board. Note that the SWx registers could
65 * technically be set to force the reference clocks to match the
66 * values that the SERDES expects (or vice versa). For now, however,
67 * we just display both values and hope the user notices when they
70 puts("SERDES Reference: ");
71 sw = QIXIS_READ(brdcfg[2]);
72 clock = (sw >> 6) & 3;
73 printf("Clock1=%sMHz ", freq[clock]);
74 clock = (sw >> 4) & 3;
75 printf("Clock2=%sMHz\n", freq[clock]);
80 int select_i2c_ch_pca9547(u8 ch)
84 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
86 puts("PCA: failed to select proper channel\n");
93 int board_early_init_r(void)
95 #ifdef CONFIG_SYS_FLASH_BASE
96 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
97 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
100 * Remap Boot flash + PROMJET region to caching-inhibited
101 * so that flash can be erased properly.
104 /* Flush d-cache and invalidate i-cache of any FLASH data */
108 /* invalidate existing TLB entry for flash + promjet */
109 disable_tlb(flash_esel);
111 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
112 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
113 0, flash_esel, BOOKE_PAGESZ_256M, 1);
116 #ifdef CONFIG_SYS_DPAA_QBMAN
119 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
124 unsigned long get_board_sys_clk(void)
126 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
128 switch (sysclk_conf & 0x0F) {
129 case QIXIS_SYSCLK_64:
131 case QIXIS_SYSCLK_83:
133 case QIXIS_SYSCLK_100:
135 case QIXIS_SYSCLK_125:
137 case QIXIS_SYSCLK_133:
139 case QIXIS_SYSCLK_150:
141 case QIXIS_SYSCLK_160:
143 case QIXIS_SYSCLK_166:
149 unsigned long get_board_ddr_clk(void)
151 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
153 switch ((ddrclk_conf & 0x30) >> 4) {
154 case QIXIS_DDRCLK_100:
156 case QIXIS_DDRCLK_125:
158 case QIXIS_DDRCLK_133:
164 #define NUM_SRDS_BANKS 2
165 int misc_init_r(void)
168 serdes_corenet_t *srds_regs =
169 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
170 u32 actual[NUM_SRDS_BANKS] = { 0 };
173 sw = QIXIS_READ(brdcfg[2]);
174 for (i = 0; i < NUM_SRDS_BANKS; i++) {
175 unsigned int clock = (sw >> (6 - 2 * i)) & 3;
178 actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
181 actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
184 actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
190 for (i = 0; i < NUM_SRDS_BANKS; i++) {
191 u32 pllcr0 = srds_regs->bank[i].pllcr0;
192 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
193 if (expected != actual[i]) {
194 printf("expects ref clk%d %sMHz, but actual is %sMHz\n",
195 i + 1, serdes_clock_to_string(expected),
196 serdes_clock_to_string(actual[i]));
203 void ft_board_setup(void *blob, bd_t *bd)
208 ft_cpu_setup(blob, bd);
210 base = getenv_bootm_low();
211 size = getenv_bootm_size();
213 fdt_fixup_memory(blob, (u64)base, (u64)size);
216 pci_of_setup(blob, bd);
219 fdt_fixup_liodn(blob);
221 #ifdef CONFIG_HAS_FSL_DR_USB
222 fdt_fixup_dr_usb(blob, bd);
225 #ifdef CONFIG_SYS_DPAA_FMAN
226 fdt_fixup_fman_ethernet(blob);
227 fdt_fixup_board_enet(blob);
231 void qixis_dump_switch(void)
235 QIXIS_WRITE(cms[0], 0x00);
236 nr_of_cfgsw = QIXIS_READ(cms[1]);
238 puts("DIP switch settings dump:\n");
239 for (i = 1; i <= nr_of_cfgsw; i++) {
240 QIXIS_WRITE(cms[0], i);
241 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
245 int board_need_mem_reset(void)
250 #ifdef CONFIG_DEEP_SLEEP
251 void board_mem_sleep_setup(void)
253 /* does not provide HW signals for power management */
254 QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2));
255 /* Disable MCKE isolation */
256 gpio_set_value(2, 0);