1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2013 Freescale Semiconductor, Inc.
10 #include <fdt_support.h>
14 #include <linux/compiler.h>
16 #include <asm/processor.h>
17 #include <asm/cache.h>
18 #include <asm/immap_85xx.h>
19 #include <asm/fsl_law.h>
20 #include <asm/fsl_serdes.h>
21 #include <asm/fsl_liodn.h>
25 #include "../common/sleep.h"
26 #include "../common/qixis.h"
28 #include "t1040qds_qixis.h"
30 DECLARE_GLOBAL_DATA_PTR;
36 struct cpu_type *cpu = gd->arch.cpu;
37 static const char *const freq[] = {"100", "125", "156.25", "161.13",
38 "122.88", "122.88", "122.88"};
41 printf("Board: %sQDS, ", cpu->name);
42 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
43 QIXIS_READ(id), QIXIS_READ(arch));
45 sw = QIXIS_READ(brdcfg[0]);
46 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
49 printf("vBank: %d\n", sw);
57 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
59 printf("FPGA: v%d (%s), build %d",
60 (int)QIXIS_READ(scver), qixis_read_tag(buf),
61 (int)qixis_read_minor());
62 /* the timestamp string contains "\n" at the end */
63 printf(" on %s", qixis_read_time(buf));
66 * Display the actual SERDES reference clocks as configured by the
67 * dip switches on the board. Note that the SWx registers could
68 * technically be set to force the reference clocks to match the
69 * values that the SERDES expects (or vice versa). For now, however,
70 * we just display both values and hope the user notices when they
73 puts("SERDES Reference: ");
74 sw = QIXIS_READ(brdcfg[2]);
75 clock = (sw >> 6) & 3;
76 printf("Clock1=%sMHz ", freq[clock]);
77 clock = (sw >> 4) & 3;
78 printf("Clock2=%sMHz\n", freq[clock]);
83 int select_i2c_ch_pca9547(u8 ch, int bus_num)
90 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
92 printf("%s: Cannot find udev for a bus %d\n", __func__,
97 ret = dm_i2c_write(dev, 0, &ch, 1);
99 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
102 puts("PCA: failed to select proper channel\n");
109 static void qe_board_setup(void)
111 u8 brdcfg15, brdcfg9;
113 if (hwconfig("qe") && hwconfig("tdm")) {
114 brdcfg15 = QIXIS_READ(brdcfg[15]);
116 * TDMRiser uses QE-TDM
117 * Route QE_TDM signals to TDM Riser slot
119 QIXIS_WRITE(brdcfg[15], brdcfg15 | 7);
120 } else if (hwconfig("qe") && hwconfig("uart")) {
121 brdcfg15 = QIXIS_READ(brdcfg[15]);
122 brdcfg9 = QIXIS_READ(brdcfg[9]);
124 * Route QE_TDM signals to UCC
125 * ProfiBus controlled by UCC3
128 QIXIS_WRITE(brdcfg[15], brdcfg15 | 2);
129 QIXIS_WRITE(brdcfg[9], brdcfg9 | 4);
133 int board_early_init_f(void)
135 #if defined(CONFIG_DEEP_SLEEP)
137 fsl_dp_disable_console();
143 int board_early_init_r(void)
145 #ifdef CONFIG_SYS_FLASH_BASE
146 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
147 int flash_esel = find_tlb_idx((void *)flashbase, 1);
150 * Remap Boot flash + PROMJET region to caching-inhibited
151 * so that flash can be erased properly.
154 /* Flush d-cache and invalidate i-cache of any FLASH data */
158 if (flash_esel == -1) {
159 /* very unlikely unless something is messed up */
160 puts("Error: Could not find TLB for FLASH BASE\n");
161 flash_esel = 2; /* give our best effort to continue */
163 /* invalidate existing TLB entry for flash + promjet */
164 disable_tlb(flash_esel);
167 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
168 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
169 0, flash_esel, BOOKE_PAGESZ_256M, 1);
171 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
176 unsigned long get_board_sys_clk(void)
178 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
180 switch (sysclk_conf & 0x0F) {
181 case QIXIS_SYSCLK_64:
183 case QIXIS_SYSCLK_83:
185 case QIXIS_SYSCLK_100:
187 case QIXIS_SYSCLK_125:
189 case QIXIS_SYSCLK_133:
191 case QIXIS_SYSCLK_150:
193 case QIXIS_SYSCLK_160:
195 case QIXIS_SYSCLK_166:
201 unsigned long get_board_ddr_clk(void)
203 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
205 switch ((ddrclk_conf & 0x30) >> 4) {
206 case QIXIS_DDRCLK_100:
208 case QIXIS_DDRCLK_125:
210 case QIXIS_DDRCLK_133:
216 #define NUM_SRDS_BANKS 2
217 int misc_init_r(void)
220 serdes_corenet_t *srds_regs =
221 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
222 u32 actual[NUM_SRDS_BANKS] = { 0 };
225 sw = QIXIS_READ(brdcfg[2]);
226 for (i = 0; i < NUM_SRDS_BANKS; i++) {
227 unsigned int clock = (sw >> (6 - 2 * i)) & 3;
230 actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
233 actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
236 actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
242 for (i = 0; i < NUM_SRDS_BANKS; i++) {
243 u32 pllcr0 = srds_regs->bank[i].pllcr0;
244 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
245 if (expected != actual[i]) {
246 printf("expects ref clk%d %sMHz, but actual is %sMHz\n",
247 i + 1, serdes_clock_to_string(expected),
248 serdes_clock_to_string(actual[i]));
257 int ft_board_setup(void *blob, bd_t *bd)
262 ft_cpu_setup(blob, bd);
264 base = env_get_bootm_low();
265 size = env_get_bootm_size();
267 fdt_fixup_memory(blob, (u64)base, (u64)size);
270 pci_of_setup(blob, bd);
273 fdt_fixup_liodn(blob);
275 #ifdef CONFIG_HAS_FSL_DR_USB
276 fsl_fdt_fixup_dr_usb(blob, bd);
279 #ifdef CONFIG_SYS_DPAA_FMAN
280 fdt_fixup_fman_ethernet(blob);
281 fdt_fixup_board_enet(blob);
287 void qixis_dump_switch(void)
291 QIXIS_WRITE(cms[0], 0x00);
292 nr_of_cfgsw = QIXIS_READ(cms[1]);
294 puts("DIP switch settings dump:\n");
295 for (i = 1; i <= nr_of_cfgsw; i++) {
296 QIXIS_WRITE(cms[0], i);
297 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
301 int board_need_mem_reset(void)