1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
12 #include <fsl_ddr_sdram.h>
13 #include <fsl_ddr_dimm_params.h>
14 #include <asm/fsl_law.h>
15 #include <asm/mpc85xx_gpio.h>
16 #include <linux/delay.h>
19 DECLARE_GLOBAL_DATA_PTR;
21 void fsl_ddr_board_options(memctl_options_t *popts,
23 unsigned int ctrl_num)
25 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
29 printf("Not supported controller number %d\n", ctrl_num);
37 /* Get clk_adjust, cpo, write_data_delay,2t, according to the board ddr
38 * freqency and n_banks specified in board_specific_parameters table.
40 ddr_freq = get_ddr_freq(0) / 1000000;
41 while (pbsp->datarate_mhz_high) {
42 if (pbsp->n_ranks == pdimm->n_ranks &&
43 (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
44 if (ddr_freq <= pbsp->datarate_mhz_high) {
45 popts->clk_adjust = pbsp->clk_adjust;
46 popts->wrlvl_start = pbsp->wrlvl_start;
47 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
48 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
57 printf("Error: board specific timing not found\n");
58 printf("for data rate %lu MT/s\n", ddr_freq);
59 printf("Trying to use the highest speed (%u) parameters\n",
60 pbsp_highest->datarate_mhz_high);
61 popts->clk_adjust = pbsp_highest->clk_adjust;
62 popts->wrlvl_start = pbsp_highest->wrlvl_start;
63 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
64 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
66 panic("DIMM is not supported by this board");
69 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
70 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
71 "wrlvl_ctrl_3 0x%x\n",
72 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
73 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
77 * Factors to consider for half-strength driver enable:
78 * - number of DIMMs installed
80 popts->half_strength_driver_enable = 1;
82 * Write leveling override
84 popts->wrlvl_override = 1;
85 popts->wrlvl_sample = 0xf;
88 * rtt and rtt_wr override
90 popts->rtt_override = 0;
92 /* Enable ZQ calibration */
95 /* DHC_EN =1, ODT = 75 Ohm */
96 #ifdef CONFIG_SYS_FSL_DDR4
97 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
98 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
99 DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
101 /* optimize cpo for erratum A-009942 */
102 popts->cpo_sample = 0x69;
104 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
105 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
109 #if defined(CONFIG_DEEP_SLEEP)
110 void board_mem_sleep_setup(void)
112 void __iomem *qixis_base = (void *)QIXIS_BASE;
114 /* does not provide HW signals for power management */
115 clrbits_8(qixis_base + 0x21, 0x2);
116 /* Disable MCKE isolation */
117 gpio_set_value(2, 0);
124 phys_size_t dram_size;
126 puts("Initializing....using SPD\n");
128 dram_size = fsl_ddr_sdram();
130 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
131 dram_size *= 0x100000;
135 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
139 gd->ram_size = dram_size;