board/freescale/t102xrdb/eth_t102xrdb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  *
   5  * Shengzhou Liu <Shengzhou.Liu@freescale.com>
   6  */
   7
   8 #include <common.h>
   9 #include <command.h>
  10 #include <fdt_support.h>
  11 #include <net.h>
  12 #include <netdev.h>
  13 #include <asm/mmu.h>
  14 #include <asm/processor.h>
  15 #include <asm/immap_85xx.h>
  16 #include <asm/fsl_law.h>
  17 #include <asm/fsl_serdes.h>
  18 #include <asm/fsl_portals.h>
  19 #include <asm/fsl_liodn.h>
  20 #include <malloc.h>
  21 #include <fm_eth.h>
  22 #include <fsl_mdio.h>
  23 #include <miiphy.h>
  24 #include <phy.h>
  25 #include <fsl_dtsec.h>
  26 #include <asm/fsl_serdes.h>
  27 #include "../common/fman.h"
  28
  29 int board_eth_init(struct bd_info *bis)
  30 {
  31 #if defined(CONFIG_FMAN_ENET)
  32         int i, interface;
  33         struct memac_mdio_info dtsec_mdio_info;
  34         struct memac_mdio_info tgec_mdio_info;
  35         struct mii_dev *dev;
  36         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  37         u32 srds_s1;
  38
  39         srds_s1 = in_be32(&gur->rcwsr[4]) &
  40                                         FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  41         srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  42
  43         dtsec_mdio_info.regs =
  44                 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
  45
  46         dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  47
  48         /* Register the 1G MDIO bus */
  49         fm_memac_mdio_init(bis, &dtsec_mdio_info);
  50
  51         tgec_mdio_info.regs =
  52                 (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
  53         tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
  54
  55         /* Register the 10G MDIO bus */
  56         fm_memac_mdio_init(bis, &tgec_mdio_info);
  57
  58         /* Set the on-board RGMII PHY address */
  59         fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
  60
  61         switch (srds_s1) {
  62 #ifdef CONFIG_TARGET_T1024RDB
  63         case 0x95:
  64                 /* set the on-board RGMII2  PHY */
  65                 fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
  66
  67                 /* set 10G XFI with Aquantia AQR105 PHY */
  68                 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
  69                 break;
  70 #endif
  71         case 0x6a:
  72         case 0x6b:
  73         case 0x77:
  74         case 0x135:
  75                 /* set the on-board 2.5G SGMII AQR105 PHY */
  76                 fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR);
  77 #ifdef CONFIG_TARGET_T1023RDB
  78                 /* set the on-board 1G SGMII RTL8211F PHY */
  79                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR);
  80 #endif
  81                 break;
  82         default:
  83                 printf("SerDes protocol 0x%x is not supported on T102xRDB\n",
  84                        srds_s1);
  85                 break;
  86         }
  87
  88         for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  89                 interface = fm_info_get_enet_if(i);
  90                 switch (interface) {
  91                 case PHY_INTERFACE_MODE_RGMII:
  92                         dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
  93                         fm_info_set_mdio(i, dev);
  94                         break;
  95                 case PHY_INTERFACE_MODE_SGMII:
  96 #if defined(CONFIG_TARGET_T1023RDB)
  97                         dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
  98 #elif defined(CONFIG_TARGET_T1024RDB)
  99                         dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
 100 #endif
 101                         fm_info_set_mdio(i, dev);
 102                         break;
 103                 case PHY_INTERFACE_MODE_SGMII_2500:
 104                         dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
 105                         fm_info_set_mdio(i, dev);
 106                         break;
 107                 default:
 108                         break;
 109                 }
 110         }
 111
 112         for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
 113                 switch (fm_info_get_enet_if(i)) {
 114                 case PHY_INTERFACE_MODE_XGMII:
 115                         dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
 116                         fm_info_set_mdio(i, dev);
 117                         break;
 118                 default:
 119                         break;
 120                 }
 121         }
 122
 123         cpu_eth_init(bis);
 124 #endif /* CONFIG_FMAN_ENET */
 125
 126         return pci_eth_init(bis);
 127 }
 128
 129 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 130                               enum fm_port port, int offset)
 131 {
 132 #if defined(CONFIG_TARGET_T1024RDB)
 133         if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) ||
 134              (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) &&
 135                         (port == FM1_DTSEC3)) {
 136                 fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4");
 137                 fdt_setprop_string(fdt, offset, "phy-connection-type",
 138                                    "sgmii-2500");
 139                 fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3");
 140         }
 141 #endif
 142 }
 143
 144 void fdt_fixup_board_enet(void *fdt)
 145 {
 146 }