3 The T1024/T1023 dual core and T1014/T1013 single core QorIQ communication processor
4 combines two or one 64-bit Power Architecture e5500 core respectively with high
5 performance datapath acceleration logic, and network peripheral bus interfaces
6 required for networking and telecommunications. This processor can be used in
7 applications such as enterprise WLAN access points, routers, switches, firewall
8 and other packet processing intensive small enterprise and branch office appliances,
9 and general-purpose embedded computing. Its high level of integration offers
10 significant performance benefits and greatly helps to simplify board design.
13 The T1024 SoC includes the following function and features:
14 - two e5500 cores, each with a private 256 KB L2 cache
15 - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
16 - Three levels of instructions: User, supervisor, and hypervisor
17 - Independent boot and reset
18 - Secure boot capability
19 - 256 KB shared L3 CoreNet platform cache (CPC)
20 - Interconnect CoreNet platform
21 - CoreNet coherency manager supporting coherent and noncoherent transactions
22 with prioritization and bandwidth allocation amongst CoreNet endpoints
23 - 150 Gbps coherent read bandwidth
24 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
25 - Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions:
26 - Packet parsing, classification, and distribution
27 - Queue management for scheduling, packet sequencing, and congestion management
28 - Cryptography Acceleration (SEC 5.x)
30 - Hardware buffer management for buffer allocation and deallocation
31 - MACSEC on DPAA-based Ethernet ports
33 - Four 1 Gbps Ethernet controllers
34 - Parallel Ethernet interfaces
35 - Two RGMII interfaces
36 - High speed peripheral interfaces
37 - Three PCI Express 2.0 controllers/ports running at up to 5 GHz
38 - One SATA controller supporting 1.5 and 3.0 Gb/s operation
39 - One QSGMII interface
40 - Four SGMII interface supporting 1000 Mbps
41 - Three SGMII interfaces supporting up to 2500 Mbps
42 - 10GbE XFI or 10Base-KR interface
43 - Additional peripheral interfaces
44 - Two USB 2.0 controllers with integrated PHY
47 - Four I2C controllers
49 - Four GPIO controllers
50 - Integrated flash controller (IFC)
51 - LCD interface (DIU) with 12 bit dual data rate
52 - Multicore programmable interrupt controller (PIC)
53 - Two 8-channel DMA engines
54 - Single source clocking implementation
55 - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
57 - 32-bit RISC controller for flexible support of the communications peripherals
58 - Serial DMA channel for receive and transmit on all serial channels
59 - Two universal communication controllers, supporting TDM, HDLC, and UART
63 T1023 is a reduced personality of T1024 without QUICC Engine, DIU, and
64 unavailable deep sleep. Rest of the blocks are almost same as T1024.
65 Differences between T1024 and T1023
75 T1024RDB board Overview
76 -----------------------
78 - Two on-board 10M/100M/1G bps RGMII ethernet ports
79 - One on-board 10G bps Base-T port.
81 - Supports 64-bit 4GB DDR3L DIMM
83 - One on-board PCIe slot.
84 - Two on-board PCIe Mini-PCIe connectors.
86 - NOR: 128MB 16-bit NOR Flash
87 - NAND: 1GB 8-bit NAND flash
88 - CPLD: for system controlling with programable header on-board
90 - Supports two USB 2.0 ports with integrated PHYs
91 - Two type A ports with 5V@1.5A per port.
93 - one SD connector supporting 1.8V/3.3V via J53.
95 - On-board 64MB SPI flash
101 T1023RDB board Overview
102 -----------------------
103 - T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz
104 - CoreNet fabric supporting coherent and noncoherent transactions with
105 prioritization and bandwidth allocation
106 - SDRAM memory: 2GB Micron MT40A512M8HX unbuffered 32-bit DDR4 w/o ECC
107 - Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC
108 - Ethernet interfaces:
109 - one 1G RGMII port on-board(RTL8211FS PHY)
110 - one 1G SGMII port on-board(RTL8211FS PHY)
111 - one 2.5G SGMII port on-board(AQR105 PHY)
112 - PCIe: Two Mini-PCIe connectors on-board.
113 - SerDes: 4 lanes up to 10.3125GHz
114 - NOR: 128MB S29GL01GS110TFIV10 Spansion NOR Flash
115 - NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash
116 - eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash.
117 - USB: one Type-A USB 2.0 port with internal PHY
118 - eSDHC: support SD/MMC and eMMC card
119 - 256Kbit M24256 I2C EEPROM
120 - RTC: Real-time clock DS1339U on I2C bus
121 - UART: one serial port on-board with RJ45 connector
122 - Debugging: JTAG/COP for T1023 debugging
125 Memory map on T1024RDB
126 ----------------------
127 Start Address End Address Description Size
128 0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
129 0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
130 0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
131 0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
132 0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
133 0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
134 0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
135 0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
136 0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
137 0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
138 0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB
139 0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB
140 0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB
141 0x0_0000_0000 0x0_ffff_ffff DDR 4GB
144 128MB NOR Flash Memory Layout
145 -----------------------------
146 Start Address End Address Definition Max size
147 0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB
148 0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB
149 0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
150 0xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB
151 0xED300000 0xEFDFFFFF rootfs (alt bank) 44MB
152 0xED000000 0xED2FFFFF Guest image #3 (alternate bank) 3MB
153 0xECD00000 0xECFFFFFF Guest image #2 (alternate bank) 3MB
154 0xECA00000 0xECCFFFFF Guest image #1 (alternate bank) 3MB
155 0xEC900000 0xEC9FFFFF HV config device tree(alt bank) 1MB
156 0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
157 0xEC700000 0xEC7FFFFF HV.uImage (alternate bank) 1MB
158 0xEC020000 0xEC6FFFFF Linux.uImage (alt bank) ~7MB
159 0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
160 0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB
161 0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB
162 0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
163 0xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB
164 0xE9300000 0xEBDFFFFF rootfs (current bank) 44MB
165 0xE9000000 0xE92FFFFF Guest image #3 (current bank) 3MB
166 0xE8D00000 0xE8FFFFFF Guest image #2 (current bank) 3MB
167 0xE8A00000 0xE8CFFFFF Guest image #1 (current bank) 3MB
168 0xE8900000 0xE89FFFFF HV config device tree(cur bank) 1MB
169 0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
170 0xE8700000 0xE87FFFFF HV.uImage (current bank) 1MB
171 0xE8020000 0xE86FFFFF Linux.uImage (current bank) ~7MB
172 0xE8000000 0xE801FFFF RCW (current bank) 128KB
175 T1024/T1023 Clock frequency
176 ---------------------------
177 BIN Core DDR Platform FMan
178 Bin1: 1400MHz 1600MT/s 400MHz 700MHz
179 Bin2: 1200MHz 1600MT/s 400MHz 600MHz
180 Bin3: 1000MHz 1600MT/s 400MHz 500MHz
183 Software configurations and board settings
184 ------------------------------------------
186 a. build NOR boot image
187 $ make T1024RDB_defconfig
189 b. program u-boot.bin image to NOR flash
190 => tftp 1000000 u-boot.bin
191 => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
193 set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
195 set SW1[1:8] = '00010110', SW2[1] = '0', SW3[4] = '0' for NOR boot
197 Switching between default bank0 and alternate bank4 on NOR flash
198 To change boot source to vbank4:
200 via software: run command 'cpld reset altbank' in u-boot.
201 via DIP-switch: set SW3[5:7] = '100'
203 via software: run command 'gpio vbank4' in u-boot.
204 via DIP-switch: set SW3[5:7] = '100'
206 To change boot source to vbank0:
208 via software: run command 'cpld reset' in u-boot.
209 via DIP-Switch: set SW3[5:7] = '000'
211 via software: run command 'gpio vbank0' in u-boot.
212 via DIP-switch: set SW3[5:7] = '000'
215 a. build PBL image for NAND boot
216 $ make T1024RDB_NAND_defconfig
218 b. program u-boot-with-spl-pbl.bin to NAND flash
219 => tftp 1000000 u-boot-with-spl-pbl.bin
220 => nand erase 0 $filesize
221 => nand write 1000000 0 $filesize
222 set SW1[1:8] = '10001000', SW2[1] = '1', SW3[4] = '1' for NAND boot
225 a. build PBL image for SPI boot
226 $ make T1024RDB_SPIFLASH_defconfig
228 b. program u-boot-with-spl-pbl.bin to SPI flash
229 => tftp 1000000 u-boot-with-spl-pbl.bin
232 => sf write 1000000 0 $filesize
233 => tftp 1000000 fsl_fman_ucode_t1024_xx.bin
234 => sf erase 100000 100000
235 => sf write 1000000 110000 20000
236 set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
239 a. build PBL image for SD boot
240 $ make T1024RDB_SDCARD_defconfig
242 b. program u-boot-with-spl-pbl.bin to SD/MMC card
243 => tftp 1000000 u-boot-with-spl-pbl.bin
244 => mmc write 1000000 8 0x800
245 => tftp 1000000 fsl_fman_ucode_t1024_xx.bin
246 => mmc write 1000000 0x820 80
247 set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
250 2-stage NAND/SPI/SD boot loader
251 -------------------------------
252 PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
253 SPL further initializes DDR using SPD and environment variables
254 and copy u-boot(768 KB) from NAND/SPI/SD device to DDR.
255 Finally SPL transers control to u-boot for futher booting.
257 SPL has following features:
258 - Executes within 256K
259 - No relocation required
261 Run time view of SPL framework
262 -------------------------------------------------
264 -------------------------------------------------
265 |SecureBoot header | 0xFFFC0000 (32KB) |
266 -------------------------------------------------
267 |GD, BD | 0xFFFC8000 (4KB) |
268 -------------------------------------------------
269 |ENV | 0xFFFC9000 (8KB) |
270 -------------------------------------------------
271 |HEAP | 0xFFFCB000 (30KB) |
272 -------------------------------------------------
273 |STACK | 0xFFFD8000 (22KB) |
274 -------------------------------------------------
275 |U-boot SPL | 0xFFFD8000 (160KB) |
276 -------------------------------------------------
278 NAND Flash memory Map on T1024RDB
279 -------------------------------------------------------------
280 Start End Definition Size
281 0x000000 0x0FFFFF u-boot 1MB(2 block)
282 0x100000 0x17FFFF u-boot env 512KB(1 block)
283 0x180000 0x1FFFFF FMAN Ucode 512KB(1 block)
284 0x200000 0x27FFFF QE Firmware 512KB(1 block)
287 NAND Flash memory Map on T1023RDB
288 ----------------------------------------------------
289 Start End Definition Size
290 0x000000 0x0FFFFF u-boot 1MB
291 0x100000 0x15FFFF u-boot env 8KB
292 0x160000 0x17FFFF FMAN Ucode 128KB
295 SD Card memory Map on T1024RDB
296 ----------------------------------------------------
297 Block #blocks Definition Size
298 0x008 2048 u-boot img 1MB
299 0x800 0016 u-boot env 8KB
300 0x820 0256 FMAN Ucode 128KB
301 0x920 0256 QE Firmware 128KB(only T1024RDB)
304 64MB SPI Flash memory Map on T102xRDB
305 ----------------------------------------------------
306 Start End Definition Size
307 0x000000 0x0FFFFF u-boot img 1MB
308 0x100000 0x101FFF u-boot env 8KB
309 0x110000 0x12FFFF FMAN Ucode 128KB
310 0x130000 0x14FFFF QE Firmware 128KB(only T1024RDB)
311 0x300000 0x3FFFFF device tree 128KB
312 0x400000 0x9FFFFF Linux kernel 6MB
313 0xa00000 0x3FFFFFF rootfs 54MB
316 For more details, please refer to T1024RDB Reference Manual
317 and Freescale QorIQ SDK Infocenter document.