1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014 Freescale Semiconductor, Inc.
10 #include <fdt_support.h>
14 #include <linux/compiler.h>
16 #include <asm/processor.h>
17 #include <asm/cache.h>
18 #include <asm/immap_85xx.h>
19 #include <asm/fsl_law.h>
20 #include <asm/fsl_serdes.h>
21 #include <asm/fsl_liodn.h>
24 #include "../common/qixis.h"
26 #include "t102xqds_qixis.h"
27 #include "../common/sleep.h"
29 DECLARE_GLOBAL_DATA_PTR;
34 struct cpu_type *cpu = gd->arch.cpu;
35 static const char *const freq[] = {"100", "125", "156.25", "100.0"};
37 u8 sw = QIXIS_READ(arch);
39 printf("Board: %sQDS, ", cpu->name);
40 printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
41 printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
48 sw = QIXIS_READ(brdcfg[0]);
49 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
52 printf("vBank: %d\n", sw);
60 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
63 printf("FPGA: v%d (%s), build %d",
64 (int)QIXIS_READ(scver), qixis_read_tag(buf),
65 (int)qixis_read_minor());
66 /* the timestamp string contains "\n" at the end */
67 printf(" on %s", qixis_read_time(buf));
69 puts("SERDES Reference: ");
70 sw = QIXIS_READ(brdcfg[2]);
71 clock = (sw >> 6) & 3;
72 printf("Clock1=%sMHz ", freq[clock]);
73 clock = (sw >> 4) & 3;
74 printf("Clock2=%sMHz\n", freq[clock]);
79 int select_i2c_ch_pca9547(u8 ch, int bus_num)
85 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
88 printf("%s: Cannot find udev for a bus %d\n", __func__,
93 ret = dm_i2c_write(dev, 0, &ch, 1);
95 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
98 puts("PCA: failed to select proper channel\n");
105 static int board_mux_lane_to_slot(void)
107 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
111 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
112 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
113 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
116 brdcfg9 = QIXIS_READ(brdcfg[9]);
117 QIXIS_WRITE(brdcfg[9], brdcfg9 | BRDCFG9_XFI_TX_DISABLE);
119 switch (srds_prtcl_s1) {
121 /* SerDes1 is not enabled */
129 QIXIS_WRITE(brdcfg[12], 0x8c);
132 QIXIS_WRITE(brdcfg[12], 0xfc);
138 QIXIS_WRITE(brdcfg[12], 0x88);
141 QIXIS_WRITE(brdcfg[12], 0xcc);
144 QIXIS_WRITE(brdcfg[12], 0xc8);
148 brdcfg9 &= ~BRDCFG9_XFI_TX_DISABLE;
149 QIXIS_WRITE(brdcfg[9], brdcfg9);
150 QIXIS_WRITE(brdcfg[12], 0x8c);
153 QIXIS_WRITE(brdcfg[12], 0x00);
159 /* Aurora, PCIe, SGMII, SATA */
160 QIXIS_WRITE(brdcfg[12], 0x04);
163 printf("WARNING: unsupported for SerDes Protocol %d\n",
171 #ifdef CONFIG_ARCH_T1024
172 static void board_mux_setup(void)
176 brdcfg15 = QIXIS_READ(brdcfg[15]);
177 brdcfg15 &= ~BRDCFG15_DIUSEL_MASK;
179 if (hwconfig_arg_cmp("pin_mux", "tdm")) {
180 /* Route QE_TDM multiplexed signals to TDM Riser slot */
181 QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_TDM);
182 QIXIS_WRITE(brdcfg[13], BRDCFG13_TDM_INTERFACE << 2);
183 QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
184 ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_TDM);
185 } else if (hwconfig_arg_cmp("pin_mux", "ucc")) {
186 /* to UCC (ProfiBus) interface */
187 QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_UCC);
188 } else if (hwconfig_arg_cmp("pin_mux", "hdmi")) {
189 /* to DVI (HDMI) encoder */
190 QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_HDMI);
191 } else if (hwconfig_arg_cmp("pin_mux", "lcd")) {
192 /* to DFP (LCD) encoder */
193 QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_LCDFM |
194 BRDCFG15_LCDPD | BRDCFG15_DIUSEL_LCD);
197 if (hwconfig_arg_cmp("adaptor", "sdxc"))
198 /* Route SPI_CS multiplexed signals to SD slot */
199 QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
200 ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_SDHC);
204 void board_retimer_ds125df111_init(void)
210 int ret, bus_num = 0;
212 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
217 /* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */
219 dm_i2c_write(dev, 0, ®, 1);
221 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC,
227 dm_i2c_write(dev, 0, ®, 1);
229 /* Access to Control/Shared register */
230 ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR,
235 dm_i2c_write(dev, 0xff, ®, 1);
237 /* Read device revision and ID */
238 dm_i2c_read(dev, 1, ®, 1);
239 debug("Retimer version id = 0x%x\n", reg);
241 /* Enable Broadcast */
243 dm_i2c_write(dev, 0xff, ®, 1);
245 /* Reset Channel Registers */
246 dm_i2c_read(dev, 0, ®, 1);
248 dm_i2c_write(dev, 0, ®, 1);
250 /* Enable override divider select and Enable Override Output Mux */
251 dm_i2c_read(dev, 9, ®, 1);
253 dm_i2c_write(dev, 9, ®, 1);
255 /* Select VCO Divider to full rate (000) */
256 dm_i2c_read(dev, 0x18, ®, 1);
258 dm_i2c_write(dev, 0x18, ®, 1);
260 /* Select active PFD MUX input as re-timed data (001) */
261 dm_i2c_read(dev, 0x1e, ®, 1);
264 dm_i2c_write(dev, 0x1e, ®, 1);
266 /* Set data rate as 10.3125 Gbps */
268 dm_i2c_write(dev, 0x60, ®, 1);
270 dm_i2c_write(dev, 0x61, ®, 1);
272 dm_i2c_write(dev, 0x62, ®, 1);
274 dm_i2c_write(dev, 0x63, ®, 1);
276 dm_i2c_write(dev, 0x64, ®, 1);
280 printf("%s: Cannot find udev for a bus %d\n", __func__,
284 /* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */
286 i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, ®, 1);
288 i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1);
290 /* Access to Control/Shared register */
292 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
294 /* Read device revision and ID */
295 i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
296 debug("Retimer version id = 0x%x\n", reg);
298 /* Enable Broadcast */
300 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
302 /* Reset Channel Registers */
303 i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
305 i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
307 /* Enable override divider select and Enable Override Output Mux */
308 i2c_read(I2C_RETIMER_ADDR, 9, 1, ®, 1);
310 i2c_write(I2C_RETIMER_ADDR, 9, 1, ®, 1);
312 /* Select VCO Divider to full rate (000) */
313 i2c_read(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
315 i2c_write(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
317 /* Select active PFD MUX input as re-timed data (001) */
318 i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
321 i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
323 /* Set data rate as 10.3125 Gbps */
325 i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
327 i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
329 i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
331 i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
333 i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
337 int board_early_init_f(void)
339 #if defined(CONFIG_DEEP_SLEEP)
341 fsl_dp_disable_console();
347 int board_early_init_r(void)
349 #ifdef CONFIG_SYS_FLASH_BASE
350 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
351 int flash_esel = find_tlb_idx((void *)flashbase, 1);
354 * Remap Boot flash + PROMJET region to caching-inhibited
355 * so that flash can be erased properly.
358 /* Flush d-cache and invalidate i-cache of any FLASH data */
362 if (flash_esel == -1) {
363 /* very unlikely unless something is messed up */
364 puts("Error: Could not find TLB for FLASH BASE\n");
365 flash_esel = 2; /* give our best effort to continue */
367 /* invalidate existing TLB entry for flash + promjet */
368 disable_tlb(flash_esel);
371 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
372 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
373 0, flash_esel, BOOKE_PAGESZ_256M, 1);
375 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
376 board_mux_lane_to_slot();
377 board_retimer_ds125df111_init();
379 /* Increase IO drive strength to address FCS error on RGMII */
380 out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR, 0xbfdb7800);
385 unsigned long get_board_sys_clk(void)
387 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
389 switch (sysclk_conf & 0x0F) {
390 case QIXIS_SYSCLK_64:
392 case QIXIS_SYSCLK_83:
394 case QIXIS_SYSCLK_100:
396 case QIXIS_SYSCLK_125:
398 case QIXIS_SYSCLK_133:
400 case QIXIS_SYSCLK_150:
402 case QIXIS_SYSCLK_160:
404 case QIXIS_SYSCLK_166:
410 unsigned long get_board_ddr_clk(void)
412 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
414 switch ((ddrclk_conf & 0x30) >> 4) {
415 case QIXIS_DDRCLK_100:
417 case QIXIS_DDRCLK_125:
419 case QIXIS_DDRCLK_133:
425 #define NUM_SRDS_PLL 2
426 int misc_init_r(void)
428 #ifdef CONFIG_ARCH_T1024
434 void fdt_fixup_spi_mux(void *blob)
438 if (hwconfig_arg_cmp("pin_mux", "tdm")) {
439 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
440 "eon,en25s64")) >= 0) {
441 fdt_del_node(blob, nodeoff);
444 /* remove tdm node */
445 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
446 "maxim,ds26522")) >= 0) {
447 fdt_del_node(blob, nodeoff);
452 int ft_board_setup(void *blob, bd_t *bd)
457 ft_cpu_setup(blob, bd);
459 base = env_get_bootm_low();
460 size = env_get_bootm_size();
462 fdt_fixup_memory(blob, (u64)base, (u64)size);
465 pci_of_setup(blob, bd);
468 fdt_fixup_liodn(blob);
470 #ifdef CONFIG_HAS_FSL_DR_USB
471 fsl_fdt_fixup_dr_usb(blob, bd);
474 #ifdef CONFIG_SYS_DPAA_FMAN
475 fdt_fixup_fman_ethernet(blob);
476 fdt_fixup_board_enet(blob);
478 fdt_fixup_spi_mux(blob);
483 void qixis_dump_switch(void)
487 QIXIS_WRITE(cms[0], 0x00);
488 nr_of_cfgsw = QIXIS_READ(cms[1]);
490 puts("DIP switch settings dump:\n");
491 for (i = 1; i <= nr_of_cfgsw; i++) {
492 QIXIS_WRITE(cms[0], i);
493 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));