1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014 Freescale Semiconductor, Inc.
10 #include <fdt_support.h>
16 #include <linux/compiler.h>
18 #include <asm/processor.h>
19 #include <asm/cache.h>
20 #include <asm/immap_85xx.h>
21 #include <asm/fsl_law.h>
22 #include <asm/fsl_serdes.h>
23 #include <asm/fsl_liodn.h>
26 #include "../common/qixis.h"
28 #include "t102xqds_qixis.h"
29 #include "../common/sleep.h"
31 DECLARE_GLOBAL_DATA_PTR;
36 struct cpu_type *cpu = gd->arch.cpu;
37 static const char *const freq[] = {"100", "125", "156.25", "100.0"};
39 u8 sw = QIXIS_READ(arch);
41 printf("Board: %sQDS, ", cpu->name);
42 printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
43 printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
50 sw = QIXIS_READ(brdcfg[0]);
51 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
54 printf("vBank: %d\n", sw);
62 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
65 printf("FPGA: v%d (%s), build %d",
66 (int)QIXIS_READ(scver), qixis_read_tag(buf),
67 (int)qixis_read_minor());
68 /* the timestamp string contains "\n" at the end */
69 printf(" on %s", qixis_read_time(buf));
71 puts("SERDES Reference: ");
72 sw = QIXIS_READ(brdcfg[2]);
73 clock = (sw >> 6) & 3;
74 printf("Clock1=%sMHz ", freq[clock]);
75 clock = (sw >> 4) & 3;
76 printf("Clock2=%sMHz\n", freq[clock]);
81 int select_i2c_ch_pca9547(u8 ch, int bus_num)
87 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
90 printf("%s: Cannot find udev for a bus %d\n", __func__,
95 ret = dm_i2c_write(dev, 0, &ch, 1);
97 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
100 puts("PCA: failed to select proper channel\n");
107 static int board_mux_lane_to_slot(void)
109 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
113 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
114 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
115 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
118 brdcfg9 = QIXIS_READ(brdcfg[9]);
119 QIXIS_WRITE(brdcfg[9], brdcfg9 | BRDCFG9_XFI_TX_DISABLE);
121 switch (srds_prtcl_s1) {
123 /* SerDes1 is not enabled */
131 QIXIS_WRITE(brdcfg[12], 0x8c);
134 QIXIS_WRITE(brdcfg[12], 0xfc);
140 QIXIS_WRITE(brdcfg[12], 0x88);
143 QIXIS_WRITE(brdcfg[12], 0xcc);
146 QIXIS_WRITE(brdcfg[12], 0xc8);
150 brdcfg9 &= ~BRDCFG9_XFI_TX_DISABLE;
151 QIXIS_WRITE(brdcfg[9], brdcfg9);
152 QIXIS_WRITE(brdcfg[12], 0x8c);
155 QIXIS_WRITE(brdcfg[12], 0x00);
161 /* Aurora, PCIe, SGMII, SATA */
162 QIXIS_WRITE(brdcfg[12], 0x04);
165 printf("WARNING: unsupported for SerDes Protocol %d\n",
173 #ifdef CONFIG_ARCH_T1024
174 static void board_mux_setup(void)
178 brdcfg15 = QIXIS_READ(brdcfg[15]);
179 brdcfg15 &= ~BRDCFG15_DIUSEL_MASK;
181 if (hwconfig_arg_cmp("pin_mux", "tdm")) {
182 /* Route QE_TDM multiplexed signals to TDM Riser slot */
183 QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_TDM);
184 QIXIS_WRITE(brdcfg[13], BRDCFG13_TDM_INTERFACE << 2);
185 QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
186 ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_TDM);
187 } else if (hwconfig_arg_cmp("pin_mux", "ucc")) {
188 /* to UCC (ProfiBus) interface */
189 QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_UCC);
190 } else if (hwconfig_arg_cmp("pin_mux", "hdmi")) {
191 /* to DVI (HDMI) encoder */
192 QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_HDMI);
193 } else if (hwconfig_arg_cmp("pin_mux", "lcd")) {
194 /* to DFP (LCD) encoder */
195 QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_LCDFM |
196 BRDCFG15_LCDPD | BRDCFG15_DIUSEL_LCD);
199 if (hwconfig_arg_cmp("adaptor", "sdxc"))
200 /* Route SPI_CS multiplexed signals to SD slot */
201 QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
202 ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_SDHC);
206 void board_retimer_ds125df111_init(void)
212 int ret, bus_num = 0;
214 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
219 /* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */
221 dm_i2c_write(dev, 0, ®, 1);
223 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC,
229 dm_i2c_write(dev, 0, ®, 1);
231 /* Access to Control/Shared register */
232 ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR,
237 dm_i2c_write(dev, 0xff, ®, 1);
239 /* Read device revision and ID */
240 dm_i2c_read(dev, 1, ®, 1);
241 debug("Retimer version id = 0x%x\n", reg);
243 /* Enable Broadcast */
245 dm_i2c_write(dev, 0xff, ®, 1);
247 /* Reset Channel Registers */
248 dm_i2c_read(dev, 0, ®, 1);
250 dm_i2c_write(dev, 0, ®, 1);
252 /* Enable override divider select and Enable Override Output Mux */
253 dm_i2c_read(dev, 9, ®, 1);
255 dm_i2c_write(dev, 9, ®, 1);
257 /* Select VCO Divider to full rate (000) */
258 dm_i2c_read(dev, 0x18, ®, 1);
260 dm_i2c_write(dev, 0x18, ®, 1);
262 /* Select active PFD MUX input as re-timed data (001) */
263 dm_i2c_read(dev, 0x1e, ®, 1);
266 dm_i2c_write(dev, 0x1e, ®, 1);
268 /* Set data rate as 10.3125 Gbps */
270 dm_i2c_write(dev, 0x60, ®, 1);
272 dm_i2c_write(dev, 0x61, ®, 1);
274 dm_i2c_write(dev, 0x62, ®, 1);
276 dm_i2c_write(dev, 0x63, ®, 1);
278 dm_i2c_write(dev, 0x64, ®, 1);
282 printf("%s: Cannot find udev for a bus %d\n", __func__,
286 /* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */
288 i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, ®, 1);
290 i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1);
292 /* Access to Control/Shared register */
294 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
296 /* Read device revision and ID */
297 i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
298 debug("Retimer version id = 0x%x\n", reg);
300 /* Enable Broadcast */
302 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
304 /* Reset Channel Registers */
305 i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
307 i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
309 /* Enable override divider select and Enable Override Output Mux */
310 i2c_read(I2C_RETIMER_ADDR, 9, 1, ®, 1);
312 i2c_write(I2C_RETIMER_ADDR, 9, 1, ®, 1);
314 /* Select VCO Divider to full rate (000) */
315 i2c_read(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
317 i2c_write(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
319 /* Select active PFD MUX input as re-timed data (001) */
320 i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
323 i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
325 /* Set data rate as 10.3125 Gbps */
327 i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
329 i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
331 i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
333 i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
335 i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
339 int board_early_init_f(void)
341 #if defined(CONFIG_DEEP_SLEEP)
343 fsl_dp_disable_console();
349 int board_early_init_r(void)
351 #ifdef CONFIG_SYS_FLASH_BASE
352 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
353 int flash_esel = find_tlb_idx((void *)flashbase, 1);
356 * Remap Boot flash + PROMJET region to caching-inhibited
357 * so that flash can be erased properly.
360 /* Flush d-cache and invalidate i-cache of any FLASH data */
364 if (flash_esel == -1) {
365 /* very unlikely unless something is messed up */
366 puts("Error: Could not find TLB for FLASH BASE\n");
367 flash_esel = 2; /* give our best effort to continue */
369 /* invalidate existing TLB entry for flash + promjet */
370 disable_tlb(flash_esel);
373 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
374 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
375 0, flash_esel, BOOKE_PAGESZ_256M, 1);
377 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
378 board_mux_lane_to_slot();
379 board_retimer_ds125df111_init();
381 /* Increase IO drive strength to address FCS error on RGMII */
382 out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR, 0xbfdb7800);
387 unsigned long get_board_sys_clk(void)
389 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
391 switch (sysclk_conf & 0x0F) {
392 case QIXIS_SYSCLK_64:
394 case QIXIS_SYSCLK_83:
396 case QIXIS_SYSCLK_100:
398 case QIXIS_SYSCLK_125:
400 case QIXIS_SYSCLK_133:
402 case QIXIS_SYSCLK_150:
404 case QIXIS_SYSCLK_160:
406 case QIXIS_SYSCLK_166:
412 unsigned long get_board_ddr_clk(void)
414 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
416 switch ((ddrclk_conf & 0x30) >> 4) {
417 case QIXIS_DDRCLK_100:
419 case QIXIS_DDRCLK_125:
421 case QIXIS_DDRCLK_133:
427 #define NUM_SRDS_PLL 2
428 int misc_init_r(void)
430 #ifdef CONFIG_ARCH_T1024
436 void fdt_fixup_spi_mux(void *blob)
440 if (hwconfig_arg_cmp("pin_mux", "tdm")) {
441 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
442 "eon,en25s64")) >= 0) {
443 fdt_del_node(blob, nodeoff);
446 /* remove tdm node */
447 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
448 "maxim,ds26522")) >= 0) {
449 fdt_del_node(blob, nodeoff);
454 int ft_board_setup(void *blob, bd_t *bd)
459 ft_cpu_setup(blob, bd);
461 base = env_get_bootm_low();
462 size = env_get_bootm_size();
464 fdt_fixup_memory(blob, (u64)base, (u64)size);
467 pci_of_setup(blob, bd);
470 fdt_fixup_liodn(blob);
472 #ifdef CONFIG_HAS_FSL_DR_USB
473 fsl_fdt_fixup_dr_usb(blob, bd);
476 #ifdef CONFIG_SYS_DPAA_FMAN
477 #ifndef CONFIG_DM_ETH
478 fdt_fixup_fman_ethernet(blob);
480 fdt_fixup_board_enet(blob);
482 fdt_fixup_spi_mux(blob);
487 void qixis_dump_switch(void)
491 QIXIS_WRITE(cms[0], 0x00);
492 nr_of_cfgsw = QIXIS_READ(cms[1]);
494 puts("DIP switch settings dump:\n");
495 for (i = 1; i <= nr_of_cfgsw; i++) {
496 QIXIS_WRITE(cms[0], i);
497 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));