board/freescale/t102xqds/t102xqds.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <command.h>
   8 #include <env.h>
   9 #include <fdt_support.h>
  10 #include <i2c.h>
  11 #include <init.h>
  12 #include <netdev.h>
  13 #include <linux/compiler.h>
  14 #include <asm/mmu.h>
  15 #include <asm/processor.h>
  16 #include <asm/cache.h>
  17 #include <asm/immap_85xx.h>
  18 #include <asm/fsl_law.h>
  19 #include <asm/fsl_serdes.h>
  20 #include <asm/fsl_liodn.h>
  21 #include <fm_eth.h>
  22 #include <hwconfig.h>
  23 #include "../common/qixis.h"
  24 #include "t102xqds.h"
  25 #include "t102xqds_qixis.h"
  26 #include "../common/sleep.h"
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 int checkboard(void)
  31 {
  32         char buf[64];
  33         struct cpu_type *cpu = gd->arch.cpu;
  34         static const char *const freq[] = {"100", "125", "156.25", "100.0"};
  35         int clock;
  36         u8 sw = QIXIS_READ(arch);
  37
  38         printf("Board: %sQDS, ", cpu->name);
  39         printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
  40         printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
  41
  42 #ifdef CONFIG_SDCARD
  43         puts("SD/MMC\n");
  44 #elif CONFIG_SPIFLASH
  45         puts("SPI\n");
  46 #else
  47         sw = QIXIS_READ(brdcfg[0]);
  48         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  49
  50         if (sw < 0x8)
  51                 printf("vBank: %d\n", sw);
  52         else if (sw == 0x8)
  53                 puts("PromJet\n");
  54         else if (sw == 0x9)
  55                 puts("NAND\n");
  56         else if (sw == 0x15)
  57                 printf("IFC Card\n");
  58         else
  59                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  60 #endif
  61
  62         printf("FPGA: v%d (%s), build %d",
  63                (int)QIXIS_READ(scver), qixis_read_tag(buf),
  64                (int)qixis_read_minor());
  65         /* the timestamp string contains "\n" at the end */
  66         printf(" on %s", qixis_read_time(buf));
  67
  68         puts("SERDES Reference: ");
  69         sw = QIXIS_READ(brdcfg[2]);
  70         clock = (sw >> 6) & 3;
  71         printf("Clock1=%sMHz ", freq[clock]);
  72         clock = (sw >> 4) & 3;
  73         printf("Clock2=%sMHz\n", freq[clock]);
  74
  75         return 0;
  76 }
  77
  78 int select_i2c_ch_pca9547(u8 ch)
  79 {
  80         int ret;
  81
  82         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  83         if (ret) {
  84                 puts("PCA: failed to select proper channel\n");
  85                 return ret;
  86         }
  87
  88         return 0;
  89 }
  90
  91 static int board_mux_lane_to_slot(void)
  92 {
  93         ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  94         u32 srds_prtcl_s1;
  95         u8 brdcfg9;
  96
  97         srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
  98                                 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  99         srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 100
 101
 102         brdcfg9 = QIXIS_READ(brdcfg[9]);
 103         QIXIS_WRITE(brdcfg[9], brdcfg9 | BRDCFG9_XFI_TX_DISABLE);
 104
 105         switch (srds_prtcl_s1) {
 106         case 0:
 107                 /* SerDes1 is not enabled */
 108                 break;
 109         case 0xd5:
 110         case 0x5b:
 111         case 0x6b:
 112         case 0x77:
 113         case 0x6f:
 114         case 0x7f:
 115                 QIXIS_WRITE(brdcfg[12], 0x8c);
 116                 break;
 117         case 0x40:
 118                 QIXIS_WRITE(brdcfg[12], 0xfc);
 119                 break;
 120         case 0xd6:
 121         case 0x5a:
 122         case 0x6a:
 123         case 0x56:
 124                 QIXIS_WRITE(brdcfg[12], 0x88);
 125                 break;
 126         case 0x47:
 127                 QIXIS_WRITE(brdcfg[12], 0xcc);
 128                 break;
 129         case 0x46:
 130                 QIXIS_WRITE(brdcfg[12], 0xc8);
 131                 break;
 132         case 0x95:
 133         case 0x99:
 134                 brdcfg9 &= ~BRDCFG9_XFI_TX_DISABLE;
 135                 QIXIS_WRITE(brdcfg[9], brdcfg9);
 136                 QIXIS_WRITE(brdcfg[12], 0x8c);
 137                 break;
 138         case 0x116:
 139                 QIXIS_WRITE(brdcfg[12], 0x00);
 140                 break;
 141         case 0x115:
 142         case 0x119:
 143         case 0x129:
 144         case 0x12b:
 145                 /* Aurora, PCIe, SGMII, SATA */
 146                 QIXIS_WRITE(brdcfg[12], 0x04);
 147                 break;
 148         default:
 149                 printf("WARNING: unsupported for SerDes Protocol %d\n",
 150                        srds_prtcl_s1);
 151                 return -1;
 152         }
 153
 154         return 0;
 155 }
 156
 157 #ifdef CONFIG_ARCH_T1024
 158 static void board_mux_setup(void)
 159 {
 160         u8 brdcfg15;
 161
 162         brdcfg15 = QIXIS_READ(brdcfg[15]);
 163         brdcfg15 &= ~BRDCFG15_DIUSEL_MASK;
 164
 165         if (hwconfig_arg_cmp("pin_mux", "tdm")) {
 166                 /* Route QE_TDM multiplexed signals to TDM Riser slot */
 167                 QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_TDM);
 168                 QIXIS_WRITE(brdcfg[13], BRDCFG13_TDM_INTERFACE << 2);
 169                 QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
 170                             ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_TDM);
 171         } else if (hwconfig_arg_cmp("pin_mux", "ucc")) {
 172                 /* to UCC (ProfiBus) interface */
 173                 QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_UCC);
 174         } else if (hwconfig_arg_cmp("pin_mux", "hdmi")) {
 175                 /* to DVI (HDMI) encoder */
 176                 QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_HDMI);
 177         } else if (hwconfig_arg_cmp("pin_mux", "lcd")) {
 178                 /* to DFP (LCD) encoder */
 179                 QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_LCDFM |
 180                             BRDCFG15_LCDPD | BRDCFG15_DIUSEL_LCD);
 181         }
 182
 183         if (hwconfig_arg_cmp("adaptor", "sdxc"))
 184                 /* Route SPI_CS multiplexed signals to SD slot */
 185                 QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
 186                             ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_SDHC);
 187 }
 188 #endif
 189
 190 void board_retimer_ds125df111_init(void)
 191 {
 192         u8 reg;
 193
 194         /* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */
 195         reg = I2C_MUX_CH7;
 196         i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &reg, 1);
 197         reg = I2C_MUX_CH5;
 198         i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
 199
 200         /* Access to Control/Shared register */
 201         reg = 0x0;
 202         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 203
 204         /* Read device revision and ID */
 205         i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
 206         debug("Retimer version id = 0x%x\n", reg);
 207
 208         /* Enable Broadcast */
 209         reg = 0x0c;
 210         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 211
 212         /* Reset Channel Registers */
 213         i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 214         reg |= 0x4;
 215         i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 216
 217         /* Enable override divider select and Enable Override Output Mux */
 218         i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
 219         reg |= 0x24;
 220         i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
 221
 222         /* Select VCO Divider to full rate (000) */
 223         i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
 224         reg &= 0x8f;
 225         i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
 226
 227         /* Select active PFD MUX input as re-timed data (001) */
 228         i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
 229         reg &= 0x3f;
 230         reg |= 0x20;
 231         i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
 232
 233         /* Set data rate as 10.3125 Gbps */
 234         reg = 0x0;
 235         i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
 236         reg = 0xb2;
 237         i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
 238         reg = 0x90;
 239         i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
 240         reg = 0xb3;
 241         i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
 242         reg = 0xcd;
 243         i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
 244 }
 245
 246 int board_early_init_f(void)
 247 {
 248 #if defined(CONFIG_DEEP_SLEEP)
 249         if (is_warm_boot())
 250                 fsl_dp_disable_console();
 251 #endif
 252
 253         return 0;
 254 }
 255
 256 int board_early_init_r(void)
 257 {
 258 #ifdef CONFIG_SYS_FLASH_BASE
 259         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 260         int flash_esel = find_tlb_idx((void *)flashbase, 1);
 261
 262         /*
 263          * Remap Boot flash + PROMJET region to caching-inhibited
 264          * so that flash can be erased properly.
 265          */
 266
 267         /* Flush d-cache and invalidate i-cache of any FLASH data */
 268         flush_dcache();
 269         invalidate_icache();
 270
 271         if (flash_esel == -1) {
 272                 /* very unlikely unless something is messed up */
 273                 puts("Error: Could not find TLB for FLASH BASE\n");
 274                 flash_esel = 2; /* give our best effort to continue */
 275         } else {
 276                 /* invalidate existing TLB entry for flash + promjet */
 277                 disable_tlb(flash_esel);
 278         }
 279
 280         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 281                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 282                 0, flash_esel, BOOKE_PAGESZ_256M, 1);
 283 #endif
 284         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 285         board_mux_lane_to_slot();
 286         board_retimer_ds125df111_init();
 287
 288         /* Increase IO drive strength to address FCS error on RGMII */
 289         out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR, 0xbfdb7800);
 290
 291         return 0;
 292 }
 293
 294 unsigned long get_board_sys_clk(void)
 295 {
 296         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 297
 298         switch (sysclk_conf & 0x0F) {
 299         case QIXIS_SYSCLK_64:
 300                 return 64000000;
 301         case QIXIS_SYSCLK_83:
 302                 return 83333333;
 303         case QIXIS_SYSCLK_100:
 304                 return 100000000;
 305         case QIXIS_SYSCLK_125:
 306                 return 125000000;
 307         case QIXIS_SYSCLK_133:
 308                 return 133333333;
 309         case QIXIS_SYSCLK_150:
 310                 return 150000000;
 311         case QIXIS_SYSCLK_160:
 312                 return 160000000;
 313         case QIXIS_SYSCLK_166:
 314                 return 166666666;
 315         }
 316         return 66666666;
 317 }
 318
 319 unsigned long get_board_ddr_clk(void)
 320 {
 321         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 322
 323         switch ((ddrclk_conf & 0x30) >> 4) {
 324         case QIXIS_DDRCLK_100:
 325                 return 100000000;
 326         case QIXIS_DDRCLK_125:
 327                 return 125000000;
 328         case QIXIS_DDRCLK_133:
 329                 return 133333333;
 330         }
 331         return 66666666;
 332 }
 333
 334 #define NUM_SRDS_PLL    2
 335 int misc_init_r(void)
 336 {
 337 #ifdef CONFIG_ARCH_T1024
 338         board_mux_setup();
 339 #endif
 340         return 0;
 341 }
 342
 343 void fdt_fixup_spi_mux(void *blob)
 344 {
 345         int nodeoff = 0;
 346
 347         if (hwconfig_arg_cmp("pin_mux", "tdm")) {
 348                 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 349                         "eon,en25s64")) >= 0) {
 350                         fdt_del_node(blob, nodeoff);
 351                 }
 352         } else {
 353                 /* remove tdm node */
 354                 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 355                         "maxim,ds26522")) >= 0) {
 356                         fdt_del_node(blob, nodeoff);
 357                 }
 358         }
 359 }
 360
 361 int ft_board_setup(void *blob, bd_t *bd)
 362 {
 363         phys_addr_t base;
 364         phys_size_t size;
 365
 366         ft_cpu_setup(blob, bd);
 367
 368         base = env_get_bootm_low();
 369         size = env_get_bootm_size();
 370
 371         fdt_fixup_memory(blob, (u64)base, (u64)size);
 372
 373 #ifdef CONFIG_PCI
 374         pci_of_setup(blob, bd);
 375 #endif
 376
 377         fdt_fixup_liodn(blob);
 378
 379 #ifdef CONFIG_HAS_FSL_DR_USB
 380         fsl_fdt_fixup_dr_usb(blob, bd);
 381 #endif
 382
 383 #ifdef CONFIG_SYS_DPAA_FMAN
 384         fdt_fixup_fman_ethernet(blob);
 385         fdt_fixup_board_enet(blob);
 386 #endif
 387         fdt_fixup_spi_mux(blob);
 388
 389         return 0;
 390 }
 391
 392 void qixis_dump_switch(void)
 393 {
 394         int i, nr_of_cfgsw;
 395
 396         QIXIS_WRITE(cms[0], 0x00);
 397         nr_of_cfgsw = QIXIS_READ(cms[1]);
 398
 399         puts("DIP switch settings dump:\n");
 400         for (i = 1; i <= nr_of_cfgsw; i++) {
 401                 QIXIS_WRITE(cms[0], i);
 402                 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 403         }
 404 }