board/t1024qds: update pin multiplexing
[platform/kernel/u-boot.git] / board / freescale / t102xqds / t102xqds.c
1 /*
2  * Copyright 2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #include <common.h>
8 #include <command.h>
9 #include <i2c.h>
10 #include <netdev.h>
11 #include <linux/compiler.h>
12 #include <asm/mmu.h>
13 #include <asm/processor.h>
14 #include <asm/cache.h>
15 #include <asm/immap_85xx.h>
16 #include <asm/fsl_law.h>
17 #include <asm/fsl_serdes.h>
18 #include <asm/fsl_portals.h>
19 #include <asm/fsl_liodn.h>
20 #include <fm_eth.h>
21 #include <hwconfig.h>
22 #include <asm/mpc85xx_gpio.h>
23 #include "../common/qixis.h"
24 #include "t102xqds.h"
25 #include "t102xqds_qixis.h"
26
27 DECLARE_GLOBAL_DATA_PTR;
28
29 int checkboard(void)
30 {
31         char buf[64];
32         struct cpu_type *cpu = gd->arch.cpu;
33         static const char *const freq[] = {"100", "125", "156.25", "100.0"};
34         int clock;
35         u8 sw = QIXIS_READ(arch);
36
37         printf("Board: %sQDS, ", cpu->name);
38         printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
39         printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
40
41 #ifdef CONFIG_SDCARD
42         puts("SD/MMC\n");
43 #elif CONFIG_SPIFLASH
44         puts("SPI\n");
45 #else
46         sw = QIXIS_READ(brdcfg[0]);
47         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
48
49         if (sw < 0x8)
50                 printf("vBank: %d\n", sw);
51         else if (sw == 0x8)
52                 puts("PromJet\n");
53         else if (sw == 0x9)
54                 puts("NAND\n");
55         else if (sw == 0x15)
56                 printf("IFC Card\n");
57         else
58                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
59 #endif
60
61         printf("FPGA: v%d (%s), build %d",
62                (int)QIXIS_READ(scver), qixis_read_tag(buf),
63                (int)qixis_read_minor());
64         /* the timestamp string contains "\n" at the end */
65         printf(" on %s", qixis_read_time(buf));
66
67         puts("SERDES Reference: ");
68         sw = QIXIS_READ(brdcfg[2]);
69         clock = (sw >> 6) & 3;
70         printf("Clock1=%sMHz ", freq[clock]);
71         clock = (sw >> 4) & 3;
72         printf("Clock2=%sMHz\n", freq[clock]);
73
74         return 0;
75 }
76
77 int select_i2c_ch_pca9547(u8 ch)
78 {
79         int ret;
80
81         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
82         if (ret) {
83                 puts("PCA: failed to select proper channel\n");
84                 return ret;
85         }
86
87         return 0;
88 }
89
90 static int board_mux_lane_to_slot(void)
91 {
92         ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
93         u32 srds_prtcl_s1;
94         u8 brdcfg9;
95
96         srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
97                                 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
98         srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
99
100
101         brdcfg9 = QIXIS_READ(brdcfg[9]);
102         QIXIS_WRITE(brdcfg[9], brdcfg9 | BRDCFG9_XFI_TX_DISABLE);
103
104         switch (srds_prtcl_s1) {
105         case 0:
106                 /* SerDes1 is not enabled */
107                 break;
108         case 0xd5:
109         case 0x5b:
110         case 0x6b:
111         case 0x77:
112         case 0x6f:
113         case 0x7f:
114                 QIXIS_WRITE(brdcfg[12], 0x8c);
115                 break;
116         case 0x40:
117                 QIXIS_WRITE(brdcfg[12], 0xfc);
118                 break;
119         case 0xd6:
120         case 0x5a:
121         case 0x6a:
122         case 0x56:
123                 QIXIS_WRITE(brdcfg[12], 0x88);
124                 break;
125         case 0x47:
126                 QIXIS_WRITE(brdcfg[12], 0xcc);
127                 break;
128         case 0x46:
129                 QIXIS_WRITE(brdcfg[12], 0xc8);
130                 break;
131         case 0x95:
132         case 0x99:
133                 brdcfg9 &= ~BRDCFG9_XFI_TX_DISABLE;
134                 QIXIS_WRITE(brdcfg[9], brdcfg9);
135                 QIXIS_WRITE(brdcfg[12], 0x8c);
136                 break;
137         case 0x116:
138                 QIXIS_WRITE(brdcfg[12], 0x00);
139                 break;
140         case 0x115:
141         case 0x119:
142         case 0x129:
143         case 0x12b:
144                 /* Aurora, PCIe, SGMII, SATA */
145                 QIXIS_WRITE(brdcfg[12], 0x04);
146                 break;
147         default:
148                 printf("WARNING: unsupported for SerDes Protocol %d\n",
149                        srds_prtcl_s1);
150                 return -1;
151         }
152
153         return 0;
154 }
155
156 #ifdef CONFIG_PPC_T1024
157 static void board_mux_setup(void)
158 {
159         u8 brdcfg15;
160
161         brdcfg15 = QIXIS_READ(brdcfg[15]);
162         brdcfg15 &= ~BRDCFG15_DIUSEL_MASK;
163
164         if (hwconfig_arg_cmp("pin_mux", "tdm")) {
165                 /* Route QE_TDM multiplexed signals to TDM Riser slot */
166                 QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_TDM);
167                 QIXIS_WRITE(brdcfg[13], BRDCFG13_TDM_INTERFACE << 2);
168                 QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
169                             ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_TDM);
170         } else if (hwconfig_arg_cmp("pin_mux", "ucc")) {
171                 /* to UCC (ProfiBus) interface */
172                 QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_UCC);
173         } else if (hwconfig_arg_cmp("pin_mux", "hdmi")) {
174                 /* to DVI (HDMI) encoder */
175                 QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_HDMI);
176         } else if (hwconfig_arg_cmp("pin_mux", "lcd")) {
177                 /* to DFP (LCD) encoder */
178                 QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_LCDFM |
179                             BRDCFG15_LCDPD | BRDCFG15_DIUSEL_LCD);
180         }
181
182         if (hwconfig_arg_cmp("adaptor", "sdxc"))
183                 /* Route SPI_CS multiplexed signals to SD slot */
184                 QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
185                             ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_SDHC);
186 }
187 #endif
188
189 int board_early_init_r(void)
190 {
191 #ifdef CONFIG_SYS_FLASH_BASE
192         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
193         int flash_esel = find_tlb_idx((void *)flashbase, 1);
194
195         /*
196          * Remap Boot flash + PROMJET region to caching-inhibited
197          * so that flash can be erased properly.
198          */
199
200         /* Flush d-cache and invalidate i-cache of any FLASH data */
201         flush_dcache();
202         invalidate_icache();
203
204         if (flash_esel == -1) {
205                 /* very unlikely unless something is messed up */
206                 puts("Error: Could not find TLB for FLASH BASE\n");
207                 flash_esel = 2; /* give our best effort to continue */
208         } else {
209                 /* invalidate existing TLB entry for flash + promjet */
210                 disable_tlb(flash_esel);
211         }
212
213         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
214                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
215                 0, flash_esel, BOOKE_PAGESZ_256M, 1);
216 #endif
217         set_liodns();
218 #ifdef CONFIG_SYS_DPAA_QBMAN
219         setup_portals();
220 #endif
221         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
222         board_mux_lane_to_slot();
223         return 0;
224 }
225
226 unsigned long get_board_sys_clk(void)
227 {
228         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
229
230         switch (sysclk_conf & 0x0F) {
231         case QIXIS_SYSCLK_64:
232                 return 64000000;
233         case QIXIS_SYSCLK_83:
234                 return 83333333;
235         case QIXIS_SYSCLK_100:
236                 return 100000000;
237         case QIXIS_SYSCLK_125:
238                 return 125000000;
239         case QIXIS_SYSCLK_133:
240                 return 133333333;
241         case QIXIS_SYSCLK_150:
242                 return 150000000;
243         case QIXIS_SYSCLK_160:
244                 return 160000000;
245         case QIXIS_SYSCLK_166:
246                 return 166666666;
247         }
248         return 66666666;
249 }
250
251 unsigned long get_board_ddr_clk(void)
252 {
253         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
254
255         switch ((ddrclk_conf & 0x30) >> 4) {
256         case QIXIS_DDRCLK_100:
257                 return 100000000;
258         case QIXIS_DDRCLK_125:
259                 return 125000000;
260         case QIXIS_DDRCLK_133:
261                 return 133333333;
262         }
263         return 66666666;
264 }
265
266 #define NUM_SRDS_PLL    2
267 int misc_init_r(void)
268 {
269 #ifdef CONFIG_PPC_T1024
270         board_mux_setup();
271 #endif
272         return 0;
273 }
274
275 void fdt_fixup_spi_mux(void *blob)
276 {
277         int nodeoff = 0;
278
279         if (hwconfig_arg_cmp("pin_mux", "tdm")) {
280                 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
281                         "eon,en25s64")) >= 0) {
282                         fdt_del_node(blob, nodeoff);
283                 }
284         } else {
285                 /* remove tdm node */
286                 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
287                         "maxim,ds26522")) >= 0) {
288                         fdt_del_node(blob, nodeoff);
289                 }
290         }
291 }
292
293 int ft_board_setup(void *blob, bd_t *bd)
294 {
295         phys_addr_t base;
296         phys_size_t size;
297
298         ft_cpu_setup(blob, bd);
299
300         base = getenv_bootm_low();
301         size = getenv_bootm_size();
302
303         fdt_fixup_memory(blob, (u64)base, (u64)size);
304
305 #ifdef CONFIG_PCI
306         pci_of_setup(blob, bd);
307 #endif
308
309         fdt_fixup_liodn(blob);
310
311 #ifdef CONFIG_HAS_FSL_DR_USB
312         fdt_fixup_dr_usb(blob, bd);
313 #endif
314
315 #ifdef CONFIG_SYS_DPAA_FMAN
316         fdt_fixup_fman_ethernet(blob);
317         fdt_fixup_board_enet(blob);
318 #endif
319         fdt_fixup_spi_mux(blob);
320
321         return 0;
322 }
323
324 void qixis_dump_switch(void)
325 {
326         int i, nr_of_cfgsw;
327
328         QIXIS_WRITE(cms[0], 0x00);
329         nr_of_cfgsw = QIXIS_READ(cms[1]);
330
331         puts("DIP switch settings dump:\n");
332         for (i = 1; i <= nr_of_cfgsw; i++) {
333                 QIXIS_WRITE(cms[0], i);
334                 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
335         }
336 }
337
338 #ifdef CONFIG_DEEP_SLEEP
339 void board_mem_sleep_setup(void)
340 {
341         /* does not provide HW signals for power management */
342         QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2));
343         /* Disable MCKE isolation */
344         gpio_set_value(2, 0);
345         udelay(1);
346 }
347 #endif