1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014 Freescale Semiconductor, Inc.
10 #include <fdt_support.h>
15 #include <linux/compiler.h>
17 #include <asm/processor.h>
18 #include <asm/cache.h>
19 #include <asm/immap_85xx.h>
20 #include <asm/fsl_law.h>
21 #include <asm/fsl_serdes.h>
22 #include <asm/fsl_liodn.h>
25 #include "../common/qixis.h"
27 #include "t102xqds_qixis.h"
28 #include "../common/sleep.h"
30 DECLARE_GLOBAL_DATA_PTR;
35 struct cpu_type *cpu = gd->arch.cpu;
36 static const char *const freq[] = {"100", "125", "156.25", "100.0"};
38 u8 sw = QIXIS_READ(arch);
40 printf("Board: %sQDS, ", cpu->name);
41 printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
42 printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
49 sw = QIXIS_READ(brdcfg[0]);
50 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
53 printf("vBank: %d\n", sw);
61 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
64 printf("FPGA: v%d (%s), build %d",
65 (int)QIXIS_READ(scver), qixis_read_tag(buf),
66 (int)qixis_read_minor());
67 /* the timestamp string contains "\n" at the end */
68 printf(" on %s", qixis_read_time(buf));
70 puts("SERDES Reference: ");
71 sw = QIXIS_READ(brdcfg[2]);
72 clock = (sw >> 6) & 3;
73 printf("Clock1=%sMHz ", freq[clock]);
74 clock = (sw >> 4) & 3;
75 printf("Clock2=%sMHz\n", freq[clock]);
80 int select_i2c_ch_pca9547(u8 ch, int bus_num)
86 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
89 printf("%s: Cannot find udev for a bus %d\n", __func__,
94 ret = dm_i2c_write(dev, 0, &ch, 1);
96 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
99 puts("PCA: failed to select proper channel\n");
106 static int board_mux_lane_to_slot(void)
108 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
112 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
113 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
114 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
117 brdcfg9 = QIXIS_READ(brdcfg[9]);
118 QIXIS_WRITE(brdcfg[9], brdcfg9 | BRDCFG9_XFI_TX_DISABLE);
120 switch (srds_prtcl_s1) {
122 /* SerDes1 is not enabled */
130 QIXIS_WRITE(brdcfg[12], 0x8c);
133 QIXIS_WRITE(brdcfg[12], 0xfc);
139 QIXIS_WRITE(brdcfg[12], 0x88);
142 QIXIS_WRITE(brdcfg[12], 0xcc);
145 QIXIS_WRITE(brdcfg[12], 0xc8);
149 brdcfg9 &= ~BRDCFG9_XFI_TX_DISABLE;
150 QIXIS_WRITE(brdcfg[9], brdcfg9);
151 QIXIS_WRITE(brdcfg[12], 0x8c);
154 QIXIS_WRITE(brdcfg[12], 0x00);
160 /* Aurora, PCIe, SGMII, SATA */
161 QIXIS_WRITE(brdcfg[12], 0x04);
164 printf("WARNING: unsupported for SerDes Protocol %d\n",
172 #ifdef CONFIG_ARCH_T1024
173 static void board_mux_setup(void)
177 brdcfg15 = QIXIS_READ(brdcfg[15]);
178 brdcfg15 &= ~BRDCFG15_DIUSEL_MASK;
180 if (hwconfig_arg_cmp("pin_mux", "tdm")) {
181 /* Route QE_TDM multiplexed signals to TDM Riser slot */
182 QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_TDM);
183 QIXIS_WRITE(brdcfg[13], BRDCFG13_TDM_INTERFACE << 2);
184 QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
185 ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_TDM);
186 } else if (hwconfig_arg_cmp("pin_mux", "ucc")) {
187 /* to UCC (ProfiBus) interface */
188 QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_UCC);
189 } else if (hwconfig_arg_cmp("pin_mux", "hdmi")) {
190 /* to DVI (HDMI) encoder */
191 QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_HDMI);
192 } else if (hwconfig_arg_cmp("pin_mux", "lcd")) {
193 /* to DFP (LCD) encoder */
194 QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_LCDFM |
195 BRDCFG15_LCDPD | BRDCFG15_DIUSEL_LCD);
198 if (hwconfig_arg_cmp("adaptor", "sdxc"))
199 /* Route SPI_CS multiplexed signals to SD slot */
200 QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
201 ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_SDHC);
205 void board_retimer_ds125df111_init(void)
211 int ret, bus_num = 0;
213 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
218 /* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */
220 dm_i2c_write(dev, 0, ®, 1);
222 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC,
228 dm_i2c_write(dev, 0, ®, 1);
230 /* Access to Control/Shared register */
231 ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR,
236 dm_i2c_write(dev, 0xff, ®, 1);
238 /* Read device revision and ID */
239 dm_i2c_read(dev, 1, ®, 1);
240 debug("Retimer version id = 0x%x\n", reg);
242 /* Enable Broadcast */
244 dm_i2c_write(dev, 0xff, ®, 1);
246 /* Reset Channel Registers */
247 dm_i2c_read(dev, 0, ®, 1);
249 dm_i2c_write(dev, 0, ®, 1);
251 /* Enable override divider select and Enable Override Output Mux */
252 dm_i2c_read(dev, 9, ®, 1);
254 dm_i2c_write(dev, 9, ®, 1);
256 /* Select VCO Divider to full rate (000) */
257 dm_i2c_read(dev, 0x18, ®, 1);
259 dm_i2c_write(dev, 0x18, ®, 1);
261 /* Select active PFD MUX input as re-timed data (001) */
262 dm_i2c_read(dev, 0x1e, ®, 1);
265 dm_i2c_write(dev, 0x1e, ®, 1);
267 /* Set data rate as 10.3125 Gbps */
269 dm_i2c_write(dev, 0x60, ®, 1);
271 dm_i2c_write(dev, 0x61, ®, 1);
273 dm_i2c_write(dev, 0x62, ®, 1);
275 dm_i2c_write(dev, 0x63, ®, 1);
277 dm_i2c_write(dev, 0x64, ®, 1);
281 printf("%s: Cannot find udev for a bus %d\n", __func__,
285 /* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */
287 i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, ®, 1);
289 i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1);
291 /* Access to Control/Shared register */
293 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
295 /* Read device revision and ID */
296 i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
297 debug("Retimer version id = 0x%x\n", reg);
299 /* Enable Broadcast */
301 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
303 /* Reset Channel Registers */
304 i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
306 i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
308 /* Enable override divider select and Enable Override Output Mux */
309 i2c_read(I2C_RETIMER_ADDR, 9, 1, ®, 1);
311 i2c_write(I2C_RETIMER_ADDR, 9, 1, ®, 1);
313 /* Select VCO Divider to full rate (000) */
314 i2c_read(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
316 i2c_write(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
318 /* Select active PFD MUX input as re-timed data (001) */
319 i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
322 i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
324 /* Set data rate as 10.3125 Gbps */
326 i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
328 i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
330 i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
332 i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
334 i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
338 int board_early_init_f(void)
340 #if defined(CONFIG_DEEP_SLEEP)
342 fsl_dp_disable_console();
348 int board_early_init_r(void)
350 #ifdef CONFIG_SYS_FLASH_BASE
351 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
352 int flash_esel = find_tlb_idx((void *)flashbase, 1);
355 * Remap Boot flash + PROMJET region to caching-inhibited
356 * so that flash can be erased properly.
359 /* Flush d-cache and invalidate i-cache of any FLASH data */
363 if (flash_esel == -1) {
364 /* very unlikely unless something is messed up */
365 puts("Error: Could not find TLB for FLASH BASE\n");
366 flash_esel = 2; /* give our best effort to continue */
368 /* invalidate existing TLB entry for flash + promjet */
369 disable_tlb(flash_esel);
372 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
373 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
374 0, flash_esel, BOOKE_PAGESZ_256M, 1);
376 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
377 board_mux_lane_to_slot();
378 board_retimer_ds125df111_init();
380 /* Increase IO drive strength to address FCS error on RGMII */
381 out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR, 0xbfdb7800);
386 unsigned long get_board_sys_clk(void)
388 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
390 switch (sysclk_conf & 0x0F) {
391 case QIXIS_SYSCLK_64:
393 case QIXIS_SYSCLK_83:
395 case QIXIS_SYSCLK_100:
397 case QIXIS_SYSCLK_125:
399 case QIXIS_SYSCLK_133:
401 case QIXIS_SYSCLK_150:
403 case QIXIS_SYSCLK_160:
405 case QIXIS_SYSCLK_166:
411 unsigned long get_board_ddr_clk(void)
413 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
415 switch ((ddrclk_conf & 0x30) >> 4) {
416 case QIXIS_DDRCLK_100:
418 case QIXIS_DDRCLK_125:
420 case QIXIS_DDRCLK_133:
426 #define NUM_SRDS_PLL 2
427 int misc_init_r(void)
429 #ifdef CONFIG_ARCH_T1024
435 void fdt_fixup_spi_mux(void *blob)
439 if (hwconfig_arg_cmp("pin_mux", "tdm")) {
440 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
441 "eon,en25s64")) >= 0) {
442 fdt_del_node(blob, nodeoff);
445 /* remove tdm node */
446 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
447 "maxim,ds26522")) >= 0) {
448 fdt_del_node(blob, nodeoff);
453 int ft_board_setup(void *blob, bd_t *bd)
458 ft_cpu_setup(blob, bd);
460 base = env_get_bootm_low();
461 size = env_get_bootm_size();
463 fdt_fixup_memory(blob, (u64)base, (u64)size);
466 pci_of_setup(blob, bd);
469 fdt_fixup_liodn(blob);
471 #ifdef CONFIG_HAS_FSL_DR_USB
472 fsl_fdt_fixup_dr_usb(blob, bd);
475 #ifdef CONFIG_SYS_DPAA_FMAN
476 fdt_fixup_fman_ethernet(blob);
477 fdt_fixup_board_enet(blob);
479 fdt_fixup_spi_mux(blob);
484 void qixis_dump_switch(void)
488 QIXIS_WRITE(cms[0], 0x00);
489 nr_of_cfgsw = QIXIS_READ(cms[1]);
491 puts("DIP switch settings dump:\n");
492 for (i = 1; i <= nr_of_cfgsw; i++) {
493 QIXIS_WRITE(cms[0], i);
494 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));