1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright 2014 Freescale Semiconductor, Inc.
6 #include <clock_legacy.h>
8 #include <env_internal.h>
15 #include <fsl_esdhc.h>
16 #include <spi_flash.h>
17 #include "../common/qixis.h"
18 #include "t102xqds_qixis.h"
19 #include "../common/spl.h"
21 DECLARE_GLOBAL_DATA_PTR;
23 phys_size_t get_effective_memsize(void)
25 return CONFIG_SYS_L3_SIZE;
28 unsigned long get_board_sys_clk(void)
30 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
32 switch (sysclk_conf & 0x0F) {
35 case QIXIS_SYSCLK_100:
37 case QIXIS_SYSCLK_125:
39 case QIXIS_SYSCLK_133:
41 case QIXIS_SYSCLK_150:
43 case QIXIS_SYSCLK_160:
45 case QIXIS_SYSCLK_166:
51 unsigned long get_board_ddr_clk(void)
53 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
55 switch ((ddrclk_conf & 0x30) >> 4) {
56 case QIXIS_DDRCLK_100:
58 case QIXIS_DDRCLK_125:
60 case QIXIS_DDRCLK_133:
66 void board_init_f(ulong bootflag)
68 u32 plat_ratio, sys_clk, ccb_clk;
69 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
71 #if defined(CONFIG_ARCH_T1040) && defined(CONFIG_SPL_NAND_BOOT)
73 * There is T1040 SoC issue where NOR, FPGA are inaccessible during
74 * NAND boot because IFC signals > IFC_AD7 are not enabled.
75 * This workaround changes RCW source to make all signals enabled.
78 #define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
80 porsr1 = in_be32(&gur->porsr1);
81 pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
82 out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);
85 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
86 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
88 /* Update GD pointer */
89 gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
93 /* initialize selected port with appropriate baud rate */
94 sys_clk = get_board_sys_clk();
95 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
96 ccb_clk = sys_clk * plat_ratio / 2;
98 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
99 ccb_clk / 16 / CONFIG_BAUDRATE);
101 #if defined(CONFIG_SPL_MMC_BOOT)
102 puts("\nSD boot...\n");
103 #elif defined(CONFIG_SPL_SPI_BOOT)
104 puts("\nSPI boot...\n");
105 #elif defined(CONFIG_SPL_NAND_BOOT)
106 puts("\nNAND boot...\n");
109 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
112 void board_init_r(gd_t *gd, ulong dest_addr)
116 bd = (bd_t *)(gd + sizeof(gd_t));
117 memset(bd, 0, sizeof(bd_t));
119 bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
120 bd->bi_memsize = CONFIG_SYS_L3_SIZE;
124 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
125 CONFIG_SPL_RELOC_MALLOC_SIZE);
126 gd->flags |= GD_FLG_FULL_MALLOC_INIT;
128 #ifdef CONFIG_SPL_NAND_BOOT
129 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
130 (uchar *)SPL_ENV_ADDR);
132 #ifdef CONFIG_SPL_MMC_BOOT
134 mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
135 (uchar *)SPL_ENV_ADDR);
137 #ifdef CONFIG_SPL_SPI_BOOT
138 fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
139 (uchar *)SPL_ENV_ADDR);
142 gd->env_addr = (ulong)(SPL_ENV_ADDR);
143 gd->env_valid = ENV_VALID;
149 #ifdef CONFIG_SPL_MMC_BOOT
151 #elif defined(CONFIG_SPL_SPI_BOOT)
153 #elif defined(CONFIG_SPL_NAND_BOOT)