1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2013-2015, Freescale Semiconductor, Inc.
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/siul.h>
11 #include <asm/arch/lpddr2.h>
12 #include <asm/arch/clock.h>
14 #include <fsl_esdhc_imx.h>
19 DECLARE_GLOBAL_DATA_PTR;
21 void setup_iomux_ddr(void)
23 lpddr2_config_iomux(DDR0);
24 lpddr2_config_iomux(DDR1);
28 void ddr_phy_init(void)
32 void ddr_ctrl_init(void)
44 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
49 static void setup_iomux_uart(void)
51 /* Muxing for linflex */
52 /* Replace the magic values after bringup */
54 /* set TXD - MSCR[12] PA12 */
55 writel(SIUL2_UART_TXD, SIUL2_MSCRn(SIUL2_UART0_TXD_PAD));
57 /* set RXD - MSCR[11] - PA11 */
58 writel(SIUL2_UART_MSCR_RXD, SIUL2_MSCRn(SIUL2_UART0_MSCR_RXD_PAD));
60 /* set RXD - IMCR[200] - 200 */
61 writel(SIUL2_UART_IMCR_RXD, SIUL2_IMCRn(SIUL2_UART0_IMCR_RXD_PAD));
64 static void setup_iomux_enet(void)
68 static void setup_iomux_i2c(void)
72 #ifdef CONFIG_SYS_USE_NAND
73 void setup_iomux_nfc(void)
78 #ifdef CONFIG_FSL_ESDHC_IMX
79 struct fsl_esdhc_cfg esdhc_cfg[1] = {
83 int board_mmc_getcd(struct mmc *mmc)
85 /* eSDHC1 is always present */
89 int board_mmc_init(struct bd_info * bis)
91 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_USDHC_CLK);
93 /* Set iomux PADS for USDHC */
95 /* PK6 pad: uSDHC clk */
96 writel(SIUL2_USDHC_PAD_CTRL_CLK, SIUL2_MSCRn(150));
97 writel(0x3, SIUL2_MSCRn(902));
99 /* PK7 pad: uSDHC CMD */
100 writel(SIUL2_USDHC_PAD_CTRL_CMD, SIUL2_MSCRn(151));
101 writel(0x3, SIUL2_MSCRn(901));
103 /* PK8 pad: uSDHC DAT0 */
104 writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(152));
105 writel(0x3, SIUL2_MSCRn(903));
107 /* PK9 pad: uSDHC DAT1 */
108 writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(153));
109 writel(0x3, SIUL2_MSCRn(904));
111 /* PK10 pad: uSDHC DAT2 */
112 writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(154));
113 writel(0x3, SIUL2_MSCRn(905));
115 /* PK11 pad: uSDHC DAT3 */
116 writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(155));
117 writel(0x3, SIUL2_MSCRn(906));
119 /* PK15 pad: uSDHC DAT4 */
120 writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(159));
121 writel(0x3, SIUL2_MSCRn(907));
123 /* PL0 pad: uSDHC DAT5 */
124 writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(160));
125 writel(0x3, SIUL2_MSCRn(908));
127 /* PL1 pad: uSDHC DAT6 */
128 writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(161));
129 writel(0x3, SIUL2_MSCRn(909));
131 /* PL2 pad: uSDHC DAT7 */
132 writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(162));
133 writel(0x3, SIUL2_MSCRn(910));
135 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
139 static void mscm_init(void)
141 struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_BASE_ADDR;
144 for (i = 0; i < MSCM_IRSPRC_NUM; i++)
145 writew(MSCM_IRSPRC_CPn_EN, &mscmir->irsprc[i]);
148 int board_phy_config(struct phy_device *phydev)
150 if (phydev->drv->config)
151 phydev->drv->config(phydev);
156 int board_early_init_f(void)
164 #ifdef CONFIG_SYS_USE_NAND
172 /* address of boot parameters */
173 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
180 puts("Board: s32v234evb\n");