2 * Copyright 2011,2012 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <linux/compiler.h>
28 #include <asm/processor.h>
29 #include <asm/cache.h>
30 #include <asm/immap_85xx.h>
31 #include <asm/fsl_law.h>
32 #include <asm/fsl_serdes.h>
33 #include <asm/fsl_portals.h>
34 #include <asm/fsl_liodn.h>
37 extern void pci_of_setup(void *blob, bd_t *bd);
41 DECLARE_GLOBAL_DATA_PTR;
46 struct cpu_type *cpu = gd->cpu;
47 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
50 printf("Board: %sRDB, ", cpu->name);
51 printf("CPLD version: %d.%d ", CPLD_READ(cpld_ver),
52 CPLD_READ(cpld_ver_sub));
54 sw = CPLD_READ(fbank_sel);
55 printf("vBank: %d\n", sw & 0x1);
58 * Display the RCW, so that no one gets confused as to what RCW
59 * we're actually using for this boot.
61 puts("Reset Configuration Word (RCW):");
62 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
63 u32 rcw = in_be32(&gur->rcwsr[i]);
66 printf("\n %08x:", i * 4);
72 * Display the actual SERDES reference clocks as configured by the
73 * dip switches on the board. Note that the SWx registers could
74 * technically be set to force the reference clocks to match the
75 * values that the SERDES expects (or vice versa). For now, however,
76 * we just display both values and hope the user notices when they
79 puts("SERDES Reference Clocks: ");
80 sw = in_8(&CPLD_SW(2)) >> 2;
81 for (i = 0; i < 2; i++) {
82 static const char * const freq[][3] = {{"0", "100", "125"},
83 {"100", "156.25", "125"}
85 unsigned int clock = (sw >> (2 * i)) & 3;
87 printf("Bank%u=%sMhz ", i+1, freq[i][clock]);
94 int board_early_init_f(void)
96 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
98 /* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */
99 setbits_be32(&gur->ddrclkdr, 0x000f000f);
104 int board_early_init_r(void)
106 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
107 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
110 * Remap Boot flash + PROMJET region to caching-inhibited
111 * so that flash can be erased properly.
114 /* Flush d-cache and invalidate i-cache of any FLASH data */
118 /* invalidate existing TLB entry for flash + promjet */
119 disable_tlb(flash_esel);
121 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
122 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
123 0, flash_esel, BOOKE_PAGESZ_256M, 1);
131 unsigned long get_board_sys_clk(unsigned long dummy)
133 u8 sysclk_conf = CPLD_READ(sysclk_sw1);
135 switch (sysclk_conf & 0x7) {
138 case CPLD_SYSCLK_100:
145 static const char *serdes_clock_to_string(u32 clock)
148 case SRDS_PLLCR0_RFCK_SEL_100:
150 case SRDS_PLLCR0_RFCK_SEL_125:
152 case SRDS_PLLCR0_RFCK_SEL_156_25:
159 #define NUM_SRDS_BANKS 2
161 int misc_init_r(void)
163 serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
164 u32 actual[NUM_SRDS_BANKS];
167 static const int freq[][3] = {
168 {0, SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_125},
169 {SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_156_25,
170 SRDS_PLLCR0_RFCK_SEL_125}
173 sw = in_8(&CPLD_SW(2)) >> 2;
174 for (i = 0; i < NUM_SRDS_BANKS; i++) {
175 unsigned int clock = (sw >> (2 * i)) & 3;
177 printf("Warning: SDREFCLK%u switch setting of '11' is "
178 "unsupported\n", i + 1);
181 if (i == 0 && clock == 0)
182 puts("Warning: SDREFCLK1 switch setting of"
183 "'00' is unsupported\n");
185 actual[i] = freq[i][clock];
188 for (i = 0; i < NUM_SRDS_BANKS; i++) {
189 u32 expected = in_be32(®s->bank[i].pllcr0);
190 expected &= SRDS_PLLCR0_RFCK_SEL_MASK;
191 if (expected != actual[i]) {
192 printf("Warning: SERDES bank %u expects reference clock"
193 " %sMHz, but actual is %sMHz\n", i + 1,
194 serdes_clock_to_string(expected),
195 serdes_clock_to_string(actual[i]));
202 void ft_board_setup(void *blob, bd_t *bd)
207 ft_cpu_setup(blob, bd);
209 base = getenv_bootm_low();
210 size = getenv_bootm_size();
212 fdt_fixup_memory(blob, (u64)base, (u64)size);
214 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
215 fdt_fixup_dr_usb(blob, bd);
219 pci_of_setup(blob, bd);
222 fdt_fixup_liodn(blob);
223 #ifdef CONFIG_SYS_DPAA_FMAN
224 fdt_fixup_fman_ethernet(blob);