1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2011,2012 Freescale Semiconductor, Inc.
9 #include <fdt_support.h>
12 #include <linux/compiler.h>
14 #include <asm/processor.h>
15 #include <asm/cache.h>
16 #include <asm/immap_85xx.h>
17 #include <asm/fsl_law.h>
18 #include <asm/fsl_serdes.h>
19 #include <asm/fsl_liodn.h>
22 extern void pci_of_setup(void *blob, bd_t *bd);
26 DECLARE_GLOBAL_DATA_PTR;
31 struct cpu_type *cpu = gd->arch.cpu;
34 printf("Board: %sRDB, ", cpu->name);
35 printf("CPLD version: %d.%d ", CPLD_READ(cpld_ver),
36 CPLD_READ(cpld_ver_sub));
38 sw = CPLD_READ(fbank_sel);
39 printf("vBank: %d\n", sw & 0x1);
42 * Display the actual SERDES reference clocks as configured by the
43 * dip switches on the board. Note that the SWx registers could
44 * technically be set to force the reference clocks to match the
45 * values that the SERDES expects (or vice versa). For now, however,
46 * we just display both values and hope the user notices when they
49 puts("SERDES Reference Clocks: ");
50 sw = in_8(&CPLD_SW(2)) >> 2;
51 for (i = 0; i < 2; i++) {
52 static const char * const freq[][3] = {{"0", "100", "125"},
53 {"100", "156.25", "125"}
55 unsigned int clock = (sw >> (2 * i)) & 3;
57 printf("Bank%u=%sMhz ", i+1, freq[i][clock]);
64 int board_early_init_f(void)
66 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
68 /* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */
69 setbits_be32(&gur->ddrclkdr, 0x000f000f);
74 #define CPLD_LANE_A_SEL 0x1
75 #define CPLD_LANE_G_SEL 0x2
76 #define CPLD_LANE_C_SEL 0x4
77 #define CPLD_LANE_D_SEL 0x8
79 void board_config_lanes_mux(void)
81 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
82 int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
83 FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
94 mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
97 mux |= CPLD_LANE_A_SEL;
100 mux |= CPLD_LANE_G_SEL;
105 mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
108 mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL;
111 printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl);
114 CPLD_WRITE(serdes_mux, mux);
117 int board_early_init_r(void)
119 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
120 int flash_esel = find_tlb_idx((void *)flashbase, 1);
123 * Remap Boot flash + PROMJET region to caching-inhibited
124 * so that flash can be erased properly.
127 /* Flush d-cache and invalidate i-cache of any FLASH data */
131 if (flash_esel == -1) {
132 /* very unlikely unless something is messed up */
133 puts("Error: Could not find TLB for FLASH BASE\n");
134 flash_esel = 2; /* give our best effort to continue */
136 /* invalidate existing TLB entry for flash + promjet */
137 disable_tlb(flash_esel);
140 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
141 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
142 0, flash_esel, BOOKE_PAGESZ_256M, 1);
144 board_config_lanes_mux();
149 unsigned long get_board_sys_clk(unsigned long dummy)
151 u8 sysclk_conf = CPLD_READ(sysclk_sw1);
153 switch (sysclk_conf & 0x7) {
156 case CPLD_SYSCLK_100:
163 #define NUM_SRDS_BANKS 2
165 int misc_init_r(void)
167 serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
168 u32 actual[NUM_SRDS_BANKS];
171 static const int freq[][3] = {
172 {0, SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_125},
173 {SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_156_25,
174 SRDS_PLLCR0_RFCK_SEL_125}
177 sw = in_8(&CPLD_SW(2)) >> 2;
178 for (i = 0; i < NUM_SRDS_BANKS; i++) {
179 unsigned int clock = (sw >> (2 * i)) & 3;
181 printf("Warning: SDREFCLK%u switch setting of '11' is "
182 "unsupported\n", i + 1);
185 if (i == 0 && clock == 0)
186 puts("Warning: SDREFCLK1 switch setting of"
187 "'00' is unsupported\n");
189 actual[i] = freq[i][clock];
192 * PC board uses a different CPLD with PB board, this CPLD
193 * has cpld_ver_sub = 1, and pcba_ver = 5. But CPLD on PB
194 * board has cpld_ver_sub = 0, and pcba_ver = 4.
196 if ((i == 1) && (CPLD_READ(cpld_ver_sub) == 1) &&
197 (CPLD_READ(pcba_ver) == 5)) {
198 /* PC board bank2 frequency */
199 actual[i] = freq[i-1][clock];
203 for (i = 0; i < NUM_SRDS_BANKS; i++) {
204 u32 expected = in_be32(®s->bank[i].pllcr0);
205 expected &= SRDS_PLLCR0_RFCK_SEL_MASK;
206 if (expected != actual[i]) {
207 printf("Warning: SERDES bank %u expects reference clock"
208 " %sMHz, but actual is %sMHz\n", i + 1,
209 serdes_clock_to_string(expected),
210 serdes_clock_to_string(actual[i]));
217 int ft_board_setup(void *blob, bd_t *bd)
222 ft_cpu_setup(blob, bd);
224 base = env_get_bootm_low();
225 size = env_get_bootm_size();
227 fdt_fixup_memory(blob, (u64)base, (u64)size);
229 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
230 fsl_fdt_fixup_dr_usb(blob, bd);
234 pci_of_setup(blob, bd);
237 fdt_fixup_liodn(blob);
238 #ifdef CONFIG_SYS_DPAA_FMAN
239 fdt_fixup_fman_ethernet(blob);