1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2011,2012 Freescale Semiconductor, Inc.
7 #include <clock_legacy.h>
10 #include <fdt_support.h>
14 #include <asm/global_data.h>
15 #include <linux/compiler.h>
17 #include <asm/processor.h>
18 #include <asm/cache.h>
19 #include <asm/immap_85xx.h>
20 #include <asm/fsl_law.h>
21 #include <asm/fsl_serdes.h>
22 #include <asm/fsl_liodn.h>
25 extern void pci_of_setup(void *blob, struct bd_info *bd);
29 DECLARE_GLOBAL_DATA_PTR;
34 struct cpu_type *cpu = gd->arch.cpu;
37 printf("Board: %sRDB, ", cpu->name);
38 printf("CPLD version: %d.%d ", CPLD_READ(cpld_ver),
39 CPLD_READ(cpld_ver_sub));
41 sw = CPLD_READ(fbank_sel);
42 printf("vBank: %d\n", sw & 0x1);
45 * Display the actual SERDES reference clocks as configured by the
46 * dip switches on the board. Note that the SWx registers could
47 * technically be set to force the reference clocks to match the
48 * values that the SERDES expects (or vice versa). For now, however,
49 * we just display both values and hope the user notices when they
52 puts("SERDES Reference Clocks: ");
53 sw = in_8(&CPLD_SW(2)) >> 2;
54 for (i = 0; i < 2; i++) {
55 static const char * const freq[][3] = {{"0", "100", "125"},
56 {"100", "156.25", "125"}
58 unsigned int clock = (sw >> (2 * i)) & 3;
60 printf("Bank%u=%sMhz ", i+1, freq[i][clock]);
67 int board_early_init_f(void)
69 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
71 /* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */
72 setbits_be32(&gur->ddrclkdr, 0x000f000f);
77 #define CPLD_LANE_A_SEL 0x1
78 #define CPLD_LANE_G_SEL 0x2
79 #define CPLD_LANE_C_SEL 0x4
80 #define CPLD_LANE_D_SEL 0x8
82 void board_config_lanes_mux(void)
84 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
85 int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
86 FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
97 mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
100 mux |= CPLD_LANE_A_SEL;
103 mux |= CPLD_LANE_G_SEL;
108 mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
111 mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL;
114 printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl);
117 CPLD_WRITE(serdes_mux, mux);
120 int board_early_init_r(void)
122 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
123 int flash_esel = find_tlb_idx((void *)flashbase, 1);
126 * Remap Boot flash + PROMJET region to caching-inhibited
127 * so that flash can be erased properly.
130 /* Flush d-cache and invalidate i-cache of any FLASH data */
134 if (flash_esel == -1) {
135 /* very unlikely unless something is messed up */
136 puts("Error: Could not find TLB for FLASH BASE\n");
137 flash_esel = 2; /* give our best effort to continue */
139 /* invalidate existing TLB entry for flash + promjet */
140 disable_tlb(flash_esel);
143 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
144 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
145 0, flash_esel, BOOKE_PAGESZ_256M, 1);
147 board_config_lanes_mux();
152 unsigned long get_board_sys_clk(void)
154 u8 sysclk_conf = CPLD_READ(sysclk_sw1);
156 switch (sysclk_conf & 0x7) {
159 case CPLD_SYSCLK_100:
166 #define NUM_SRDS_BANKS 2
168 int misc_init_r(void)
170 serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
171 u32 actual[NUM_SRDS_BANKS];
174 static const int freq[][3] = {
175 {0, SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_125},
176 {SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_156_25,
177 SRDS_PLLCR0_RFCK_SEL_125}
180 sw = in_8(&CPLD_SW(2)) >> 2;
181 for (i = 0; i < NUM_SRDS_BANKS; i++) {
182 unsigned int clock = (sw >> (2 * i)) & 3;
184 printf("Warning: SDREFCLK%u switch setting of '11' is "
185 "unsupported\n", i + 1);
188 if (i == 0 && clock == 0)
189 puts("Warning: SDREFCLK1 switch setting of"
190 "'00' is unsupported\n");
192 actual[i] = freq[i][clock];
195 * PC board uses a different CPLD with PB board, this CPLD
196 * has cpld_ver_sub = 1, and pcba_ver = 5. But CPLD on PB
197 * board has cpld_ver_sub = 0, and pcba_ver = 4.
199 if ((i == 1) && (CPLD_READ(cpld_ver_sub) == 1) &&
200 (CPLD_READ(pcba_ver) == 5)) {
201 /* PC board bank2 frequency */
202 actual[i] = freq[i-1][clock];
206 for (i = 0; i < NUM_SRDS_BANKS; i++) {
207 u32 expected = in_be32(®s->bank[i].pllcr0);
208 expected &= SRDS_PLLCR0_RFCK_SEL_MASK;
209 if (expected != actual[i]) {
210 printf("Warning: SERDES bank %u expects reference clock"
211 " %sMHz, but actual is %sMHz\n", i + 1,
212 serdes_clock_to_string(expected),
213 serdes_clock_to_string(actual[i]));
220 int ft_board_setup(void *blob, struct bd_info *bd)
225 ft_cpu_setup(blob, bd);
227 base = env_get_bootm_low();
228 size = env_get_bootm_size();
230 fdt_fixup_memory(blob, (u64)base, (u64)size);
232 #if defined(CONFIG_HAS_FSL_DR_USB)
233 fsl_fdt_fixup_dr_usb(blob, bd);
237 pci_of_setup(blob, bd);
240 fdt_fixup_liodn(blob);
241 #ifdef CONFIG_SYS_DPAA_FMAN
242 #ifndef CONFIG_DM_ETH
243 fdt_fixup_fman_ethernet(blob);