board/freescale/p2041rdb/ddr.c

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #include <common.h>
  10 #include <i2c.h>
  11 #include <hwconfig.h>
  12 #include <asm/mmu.h>
  13 #include <asm/fsl_ddr_sdram.h>
  14 #include <asm/fsl_ddr_dimm_params.h>
  15 #include <asm/fsl_law.h>
  16
  17 typedef struct {
  18         u32 datarate_mhz_low;
  19         u32 datarate_mhz_high;
  20         u32 n_ranks;
  21         u32 clk_adjust;
  22         u32 wrlvl_start;
  23         u32 cpo;
  24         u32 write_data_delay;
  25         u32 force_2T;
  26 } board_specific_parameters_t;
  27
  28 /*
  29  * ranges for parameters:
  30  *  wr_data_delay = 0-6
  31  *  clk adjust = 0-8
  32  *  cpo 2-0x1E (30)
  33  */
  34 const board_specific_parameters_t board_specific_parameters[] = {
  35         /*
  36          * memory controller 0
  37          *  lo|  hi|  num|  clk| wrlvl | cpo  |wrdata|2T
  38          * mhz| mhz|ranks|adjst| start | delay|
  39          */
  40         {  1017, 1116,    2,    4,     6,   0xff,    2,  0},
  41 };
  42
  43 void fsl_ddr_board_options(memctl_options_t *popts,
  44                                 dimm_params_t *pdimm,
  45                                 unsigned int ctrl_num)
  46 {
  47         const board_specific_parameters_t *pbsp =
  48                                 &board_specific_parameters[0];
  49         u32 num_params = ARRAY_SIZE(board_specific_parameters);
  50         u32 i;
  51         ulong ddr_freq;
  52
  53         /*
  54          * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
  55          * freqency and n_banks specified in board_specific_parameters table.
  56          */
  57         ddr_freq = get_ddr_freq(0) / 1000000;
  58         for (i = 0; i < num_params; i++) {
  59                 if (ddr_freq >= pbsp->datarate_mhz_low &&
  60                         ddr_freq <= pbsp->datarate_mhz_high &&
  61                         pdimm[0].n_ranks == pbsp->n_ranks) {
  62                         popts->cpo_override = pbsp->cpo;
  63                         popts->write_data_delay = pbsp->write_data_delay;
  64                         popts->clk_adjust = pbsp->clk_adjust;
  65                         popts->wrlvl_start = pbsp->wrlvl_start;
  66                         popts->twoT_en = pbsp->force_2T;
  67                         break;
  68                 }
  69                 pbsp++;
  70         }
  71
  72         if (i == num_params) {
  73                 printf("Warning: board specific timing not found "
  74                         "for data rate %lu MT/s!\n", ddr_freq);
  75         }
  76
  77         /*
  78          * Factors to consider for half-strength driver enable:
  79          *      - number of DIMMs installed
  80          */
  81         popts->half_strength_driver_enable = 0;
  82         /* Write leveling override */
  83         popts->wrlvl_override = 1;
  84         popts->wrlvl_sample = 0xf;
  85
  86         /* Rtt and Rtt_WR override */
  87         popts->rtt_override = 0;
  88
  89         /* Enable ZQ calibration */
  90         popts->zq_en = 1;
  91
  92         /* DHC_EN =1, ODT = 60 Ohm */
  93         popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
  94 }
  95
  96 phys_size_t initdram(int board_type)
  97 {
  98         phys_size_t dram_size = 0;
  99
 100         puts("Initializing....");
 101
 102         if (fsl_use_spd()) {
 103                 puts("using SPD\n");
 104                 dram_size = fsl_ddr_sdram();
 105         } else {
 106                 puts("no SPD and fixed parameters\n");
 107                 return dram_size;
 108         }
 109
 110         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 111         dram_size *= 0x100000;
 112
 113         debug("    DDR: ");
 114         return dram_size;
 115 }