board/freescale/p2041rdb/cpld.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /**
   3  * Copyright 2011 Freescale Semiconductor
   4  * Author: Mingkai Hu <Mingkai.hu@freescale.com>
   5  *
   6  * This file provides support for the board-specific CPLD used on some Freescale
   7  * reference boards.
   8  *
   9  * The following macros need to be defined:
  10  *
  11  * CPLD_BASE - The virtual address of the base of the CPLD register map
  12  */
  13
  14 #include <common.h>
  15 #include <command.h>
  16 #include <asm/io.h>
  17
  18 #include "cpld.h"
  19
  20 static u8 __cpld_read(unsigned int reg)
  21 {
  22         void *p = (void *)CPLD_BASE;
  23
  24         return in_8(p + reg);
  25 }
  26 u8 cpld_read(unsigned int reg) __attribute__((weak, alias("__cpld_read")));
  27
  28 static void __cpld_write(unsigned int reg, u8 value)
  29 {
  30         void *p = (void *)CPLD_BASE;
  31
  32         out_8(p + reg, value);
  33 }
  34 void cpld_write(unsigned int reg, u8 value)
  35         __attribute__((weak, alias("__cpld_write")));
  36
  37 /*
  38  * Reset the board. This honors the por_cfg registers.
  39  */
  40 void __cpld_reset(void)
  41 {
  42         CPLD_WRITE(system_rst, 1);
  43 }
  44 void cpld_reset(void) __attribute__((weak, alias("__cpld_reset")));
  45
  46 /**
  47  * Set the boot bank to the alternate bank
  48  */
  49 void __cpld_set_altbank(void)
  50 {
  51         u8 reg5 = CPLD_READ(sw_ctl_on);
  52
  53         CPLD_WRITE(sw_ctl_on, reg5 | CPLD_SWITCH_BANK_ENABLE);
  54         CPLD_WRITE(fbank_sel, 1);
  55         CPLD_WRITE(system_rst, 1);
  56 }
  57 void cpld_set_altbank(void)
  58         __attribute__((weak, alias("__cpld_set_altbank")));
  59
  60 /**
  61  * Set the boot bank to the default bank
  62  */
  63 void __cpld_set_defbank(void)
  64 {
  65         CPLD_WRITE(system_rst_default, 1);
  66 }
  67 void cpld_set_defbank(void)
  68         __attribute__((weak, alias("__cpld_set_defbank")));
  69
  70 #ifdef DEBUG
  71 static void cpld_dump_regs(void)
  72 {
  73         printf("cpld_ver        = 0x%02x\n", CPLD_READ(cpld_ver));
  74         printf("cpld_ver_sub    = 0x%02x\n", CPLD_READ(cpld_ver_sub));
  75         printf("pcba_ver        = 0x%02x\n", CPLD_READ(pcba_ver));
  76         printf("system_rst      = 0x%02x\n", CPLD_READ(system_rst));
  77         printf("sw_ctl_on       = 0x%02x\n", CPLD_READ(sw_ctl_on));
  78         printf("por_cfg         = 0x%02x\n", CPLD_READ(por_cfg));
  79         printf("switch_strobe   = 0x%02x\n", CPLD_READ(switch_strobe));
  80         printf("jtag_sel        = 0x%02x\n", CPLD_READ(jtag_sel));
  81         printf("sdbank1_clk     = 0x%02x\n", CPLD_READ(sdbank1_clk));
  82         printf("sdbank2_clk     = 0x%02x\n", CPLD_READ(sdbank2_clk));
  83         printf("fbank_sel       = 0x%02x\n", CPLD_READ(fbank_sel));
  84         printf("serdes_mux      = 0x%02x\n", CPLD_READ(serdes_mux));
  85         printf("SW[2]           = 0x%02x\n", in_8(&CPLD_SW(2)));
  86         putc('\n');
  87 }
  88 #endif
  89
  90 int cpld_cmd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  91 {
  92         int rc = 0;
  93
  94         if (argc <= 1)
  95                 return cmd_usage(cmdtp);
  96
  97         if (strcmp(argv[1], "reset") == 0) {
  98                 if (strcmp(argv[2], "altbank") == 0)
  99                         cpld_set_altbank();
 100                 else
 101                         cpld_set_defbank();
 102         } else if (strcmp(argv[1], "lane_mux") == 0) {
 103                 u32 lane = hextoul(argv[2], NULL);
 104                 u8 val = (u8)hextoul(argv[3], NULL);
 105                 u8 reg = CPLD_READ(serdes_mux);
 106
 107                 switch (lane) {
 108                 case 0x6:
 109                         reg &= ~SERDES_MUX_LANE_6_MASK;
 110                         reg |= val << SERDES_MUX_LANE_6_SHIFT;
 111                         break;
 112                 case 0xa:
 113                         reg &= ~SERDES_MUX_LANE_A_MASK;
 114                         reg |= val << SERDES_MUX_LANE_A_SHIFT;
 115                         break;
 116                 case 0xc:
 117                         reg &= ~SERDES_MUX_LANE_C_MASK;
 118                         reg |= val << SERDES_MUX_LANE_C_SHIFT;
 119                         break;
 120                 case 0xd:
 121                         reg &= ~SERDES_MUX_LANE_D_MASK;
 122                         reg |= val << SERDES_MUX_LANE_D_SHIFT;
 123                         break;
 124                 default:
 125                         printf("Invalid value\n");
 126                         break;
 127                 }
 128
 129                 CPLD_WRITE(serdes_mux, reg);
 130 #ifdef DEBUG
 131         } else if (strcmp(argv[1], "dump") == 0) {
 132                 cpld_dump_regs();
 133 #endif
 134         } else
 135                 rc = cmd_usage(cmdtp);
 136
 137         return rc;
 138 }
 139
 140 U_BOOT_CMD(
 141         cpld_cmd, CONFIG_SYS_MAXARGS, 1, cpld_cmd,
 142         "Reset the board or pin mulexing selection using the CPLD sequencer",
 143         "reset - hard reset to default bank\n"
 144         "cpld_cmd reset altbank - reset to alternate bank\n"
 145         "cpld_cmd lane_mux <lane> <mux_value> - set multiplexed lane pin\n"
 146         "       lane 6: 0 -> slot1\n"
 147         "               1 -> SGMII (Default)\n"
 148         "       lane a: 0 -> slot2\n"
 149         "               1 -> AURORA (Default)\n"
 150         "       lane c: 0 -> slot2\n"
 151         "               1 -> SATA0 (Default)\n"
 152         "       lane d: 0 -> slot2\n"
 153         "               1 -> SATA1 (Default)\n"
 154 #ifdef DEBUG
 155         "cpld_cmd dump - display the CPLD registers\n"
 156 #endif
 157         );