board/freescale/p2020ds/ddr.c

   1 /*
   2  * Copyright 2008-2009 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #include <common.h>
  10 #include <i2c.h>
  11
  12 #include <asm/fsl_ddr_sdram.h>
  13 #include <asm/fsl_ddr_dimm_params.h>
  14
  15 static void get_spd(generic_spd_eeprom_t *spd, unsigned char i2c_address)
  16 {
  17         i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t));
  18 }
  19
  20 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
  21                       unsigned int ctrl_num)
  22 {
  23         unsigned int i;
  24         unsigned int i2c_address = 0;
  25
  26         for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
  27                 if (ctrl_num == 0 && i == 0)
  28                         i2c_address = SPD_EEPROM_ADDRESS1;
  29                 get_spd(&(ctrl_dimms_spd[i]), i2c_address);
  30         }
  31 }
  32
  33 typedef struct {
  34         u32 datarate_mhz_low;
  35         u32 datarate_mhz_high;
  36         u32 n_ranks;
  37         u32 clk_adjust;
  38         u32 cpo;
  39         u32 write_data_delay;
  40         u32 force_2T;
  41 } board_specific_parameters_t;
  42
  43 /* ranges for parameters:
  44  *  wr_data_delay = 0-6
  45  *  clk adjust = 0-8
  46  *  cpo 2-0x1E (30)
  47  */
  48
  49 const board_specific_parameters_t board_specific_parameters[][20] = {
  50         {
  51         /*      memory controller 0                     */
  52         /*        lo|  hi|  num|  clk| cpo|wrdata|2T    */
  53         /*       mhz| mhz|ranks|adjst|    | delay|      */
  54 #ifdef CONFIG_FSL_DDR2
  55                 {  0, 333,    2,    4,   0x1f,    2,  0},
  56                 {334, 400,    2,    4,   0x1f,    2,  0},
  57                 {401, 549,    2,    4,   0x1f,    2,  0},
  58                 {550, 680,    2,    4,   0x1f,    3,  0},
  59                 {681, 850,    2,    4,   0x1f,    4,  0},
  60                 {  0, 333,    1,    4,   0x1f,    2,  0},
  61                 {334, 400,    1,    4,   0x1f,    2,  0},
  62                 {401, 549,    1,    4,   0x1f,    2,  0},
  63                 {550, 680,    1,    4,   0x1f,    3,  0},
  64                 {681, 850,    1,    4,   0x1f,    4,  0}
  65 #else
  66                 {  0, 850,    2,    6,   0x1f,    4,  0},
  67                 {  0, 850,    1,    4,   0x1f,    4,  0}
  68 #endif
  69         },
  70 };
  71
  72 void fsl_ddr_board_options(memctl_options_t *popts,
  73                                 dimm_params_t *pdimm,
  74                                 unsigned int ctrl_num)
  75 {
  76         const board_specific_parameters_t *pbsp =
  77                                 &(board_specific_parameters[ctrl_num][0]);
  78         u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
  79                                 sizeof(board_specific_parameters[0][0]);
  80         u32 i;
  81         ulong ddr_freq;
  82
  83         /* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
  84          * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
  85          * there are two dimms in the controller, set odt_rd_cfg to 3 and
  86          * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
  87          */
  88         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  89                         popts->cs_local_opts[i].odt_rd_cfg = 0;
  90                         popts->cs_local_opts[i].odt_wr_cfg = 1;
  91         }
  92
  93         /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
  94          * freqency and n_banks specified in board_specific_parameters table.
  95          */
  96         ddr_freq = get_ddr_freq(0) / 1000000;
  97         for (i = 0; i < num_params; i++) {
  98                 if (ddr_freq >= pbsp->datarate_mhz_low &&
  99                     ddr_freq <= pbsp->datarate_mhz_high &&
 100                     pdimm->n_ranks == pbsp->n_ranks) {
 101                         popts->clk_adjust = pbsp->clk_adjust;
 102                         popts->cpo_override = pbsp->cpo;
 103                         popts->write_data_delay = pbsp->write_data_delay;
 104                         popts->twoT_en = pbsp->force_2T;
 105                 }
 106                 pbsp++;
 107         }
 108
 109         /*
 110          * Factors to consider for half-strength driver enable:
 111          *      - number of DIMMs installed
 112          */
 113         popts->half_strength_driver_enable = 0;
 114         popts->wrlvl_en = 1;
 115         /* Write leveling override */
 116         popts->wrlvl_override = 1;
 117         popts->wrlvl_sample = 0xa;
 118         popts->wrlvl_start = 0x8;
 119         /* Rtt and Rtt_WR override */
 120         popts->rtt_override = 1;
 121         popts->rtt_override_value = DDR3_RTT_120_OHM;
 122         popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
 123 }