1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
9 struct fsl_e_tlb_entry tlb_table[] = {
10 /* TLB 0 - for temp stack in cache */
11 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
12 CONFIG_SYS_INIT_RAM_ADDR_PHYS,
13 MAS3_SX|MAS3_SW|MAS3_SR, 0,
14 0, 0, BOOKE_PAGESZ_4K, 0),
15 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
16 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
17 MAS3_SX|MAS3_SW|MAS3_SR, 0,
18 0, 0, BOOKE_PAGESZ_4K, 0),
19 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
20 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
21 MAS3_SX|MAS3_SW|MAS3_SR, 0,
22 0, 0, BOOKE_PAGESZ_4K, 0),
23 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
24 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
25 MAS3_SX|MAS3_SW|MAS3_SR, 0,
26 0, 0, BOOKE_PAGESZ_4K, 0),
29 /* *I*** - Covers boot page */
30 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
31 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
32 0, 0, BOOKE_PAGESZ_4K, 1),
35 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
36 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
37 0, 1, BOOKE_PAGESZ_1M, 1),
39 #ifndef CONFIG_SPL_BUILD
40 /* W**G* - Flash/promjet, localbus */
41 /* This will be changed to *I*G* after relocation to RAM. */
42 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
43 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
44 0, 2, BOOKE_PAGESZ_64M, 1),
47 /* *I*G* - PCI memory 1.5G */
48 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
49 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
50 0, 3, BOOKE_PAGESZ_1G, 1),
52 /* *I*G* - PCI I/O effective: 192K */
53 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
54 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
55 0, 4, BOOKE_PAGESZ_256K, 1),
58 #ifdef CONFIG_VSC7385_ENET
59 /* *I*G - VSC7385 Switch */
60 SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS,
61 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
62 0, 5, BOOKE_PAGESZ_1M, 1),
66 SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
67 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
68 0, 6, BOOKE_PAGESZ_1M, 1),
70 #ifdef CONFIG_SYS_NAND_BASE
72 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
73 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
74 0, 7, BOOKE_PAGESZ_1M, 1),
77 #if defined(CONFIG_SYS_RAMBOOT) || !CONFIG_IS_ENABLED(COMMON_INIT_DDR)
78 /* **M** - 1G DDR for eSDHC/eSPI/NAND boot */
79 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
80 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
81 0, 8, BOOKE_PAGESZ_1G, 1),
83 #if defined(CONFIG_TARGET_P1020RDB_PD)
84 /* **M** - 2G DDR on P1020MBG, map the second 1G */
85 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
86 CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
87 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
88 0, 9, BOOKE_PAGESZ_1G, 1),
90 #endif /* RAMBOOT/SPL */
92 #ifdef CONFIG_SYS_INIT_L2_ADDR
94 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
95 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
96 0, 11, BOOKE_PAGESZ_256K, 1),
97 #if CONFIG_SYS_L2_SIZE >= (256 << 10)
98 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
99 CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
100 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
101 0, 12, BOOKE_PAGESZ_256K, 1)
106 int num_tlb_entries = ARRAY_SIZE(tlb_table);