2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/processor.h>
30 #include <asm/cache.h>
31 #include <asm/immap_85xx.h>
32 #include <asm/fsl_pci.h>
33 #include <asm/fsl_ddr_sdram.h>
35 #include <asm/fsl_law.h>
36 #include <asm/fsl_lbc.h>
40 #include <fdt_support.h>
45 #include <asm/fsl_serdes.h>
50 #define GPIO_GETH_SW_PORT 1
51 #define GPIO_GETH_SW_PIN 29
52 #define GPIO_GETH_SW_DATA (1 << (31 - GPIO_GETH_SW_PIN))
54 #define GPIO_SLIC_PORT 1
55 #define GPIO_SLIC_PIN 30
56 #define GPIO_SLIC_DATA (1 << (31 - GPIO_SLIC_PIN))
59 #if defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB)
60 #define PCA_IOPORT_I2C_ADDR 0x23
61 #define PCA_IOPORT_OUTPUT_CMD 0x2
62 #define PCA_IOPORT_CFG_CMD 0x6
63 #define PCA_IOPORT_QE_PIN_ENABLE 0xf8
64 #define PCA_IOPORT_QE_TDM_ENABLE 0xf6
67 const qe_iop_conf_t qe_iop_conf_tab[] = {
69 {1, 1, 2, 0, 0}, /* GPIO7/PB1 - LOAD_DEFAULT_N */
71 {1, 8, 1, 1, 0}, /* GPIO10/PB8 - DDR_RST */
73 {0, 15, 1, 0, 0}, /* GPIO11/A15 - WDI */
74 {GPIO_GETH_SW_PORT, GPIO_GETH_SW_PIN, 1, 0, 0}, /* RST_GETH_SW_N */
75 {GPIO_SLIC_PORT, GPIO_SLIC_PIN, 1, 0, 0}, /* RST_SLIC_N */
77 #ifdef CONFIG_P1025RDB
79 {1, 19, 1, 0, 1}, /* QE_MUX_MDC */
82 {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */
85 {0, 23, 2, 0, 2}, /* CLK12 */
86 {0, 24, 2, 0, 1}, /* CLK9 */
87 {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
88 {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
89 {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
90 {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
91 {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
92 {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
93 {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
94 {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
95 {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
96 {0, 13, 1, 0, 2}, /* ENET1_TX_ER */
97 {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */
98 {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */
99 {0, 17, 2, 0, 2}, /* ENET1_CRS */
100 {0, 16, 2, 0, 2}, /* ENET1_COL */
103 {1, 11, 2, 0, 1}, /* CLK13 */
104 {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
105 {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
106 {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
107 {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
108 {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */
109 {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */
110 {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */
113 {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
126 u8 status_led; /* offset: 0x8 */
127 u8 fxo_led; /* offset: 0x9 */
128 u8 fxs_led; /* offset: 0xa */
130 u8 system_rst; /* offset: 0xd */
136 #define CPLD_WD_CFG 0x03
137 #define CPLD_RST_BSW 0x00
138 #define CPLD_RST_BWD 0x00
139 #define CPLD_BYPASS_EN 0x03
140 #define CPLD_STATUS_LED 0x01
141 #define CPLD_FXO_LED 0x01
142 #define CPLD_FXS_LED 0x0F
143 #define CPLD_SYS_RST 0x00
145 void board_cpld_init(void)
147 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
149 out_8(&cpld_data->wd_cfg, CPLD_WD_CFG);
150 out_8(&cpld_data->status_led, CPLD_STATUS_LED);
151 out_8(&cpld_data->fxo_led, CPLD_FXO_LED);
152 out_8(&cpld_data->fxs_led, CPLD_FXS_LED);
153 out_8(&cpld_data->system_rst, CPLD_SYS_RST);
156 void board_gpio_init(void)
159 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
160 par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
162 /* Enable VSC7385 switch */
163 setbits_be32(&par_io[GPIO_GETH_SW_PORT].cpdat, GPIO_GETH_SW_DATA);
166 setbits_be32(&par_io[GPIO_SLIC_PORT].cpdat, GPIO_SLIC_DATA);
169 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
172 * GPIO10 DDR Reset, open drain
173 * GPIO7 LOAD_DEFAULT_N Input
174 * GPIO11 WDI (watchdog input)
175 * GPIO12 Ethernet Switch Reset
179 setbits_be32(&pgpio->gpdir, 0x02130000);
180 #if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL)
181 /* init DDR3 reset signal */
182 setbits_be32(&pgpio->gpdir, 0x00200000);
183 setbits_be32(&pgpio->gpodr, 0x00200000);
184 clrbits_be32(&pgpio->gpdat, 0x00200000);
186 setbits_be32(&pgpio->gpdat, 0x00200000);
188 clrbits_be32(&pgpio->gpdir, 0x00200000);
191 #ifdef CONFIG_VSC7385_ENET
192 /* reset VSC7385 Switch */
193 setbits_be32(&pgpio->gpdir, 0x00080000);
194 setbits_be32(&pgpio->gpdat, 0x00080000);
199 setbits_be32(&pgpio->gpdir, 0x00040000);
200 setbits_be32(&pgpio->gpdat, 0x00040000);
205 int board_early_init_f(void)
207 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
209 setbits_be32(&gur->pmuxcr,
210 (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
211 clrbits_be32(&gur->sdhcdcr, SDHCDCR_CD_INV);
213 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
214 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_ENA);
224 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
225 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
226 u8 in, out, io_config, val;
228 printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n", CONFIG_BOARDNAME,
229 in_8(&cpld_data->cpld_rev_major) & 0x0F,
230 in_8(&cpld_data->cpld_rev_minor) & 0x0F,
231 in_8(&cpld_data->pcba_rev) & 0x0F);
233 /* Initialize i2c early for rom_loc and flash bank information */
234 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
236 if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
237 i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
238 i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) {
239 printf("Error reading i2c boot information!\n");
240 return 0; /* Don't want to hang() on this error */
243 val = (in & io_config) | (out & (~io_config));
246 if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) {
249 } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SPI) {
252 #ifdef __SW_BOOT_NAND
253 } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_NAND) {
256 #ifdef __SW_BOOT_PCIE
257 } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_PCIE) {
262 puts("nor lower bank");
264 puts("nor upper bank");
269 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
270 puts("SD/MMC : 8-bit Mode\n");
271 puts("eSPI : Disabled\n");
273 puts("SD/MMC : 4-bit Mode\n");
274 puts("eSPI : Enabled\n");
281 void pci_init_board(void)
283 fsl_pcie_init_board(0);
287 int board_early_init_r(void)
289 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
290 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
293 * Remap Boot flash region to caching-inhibited
294 * so that flash can be erased properly.
297 /* Flush d-cache and invalidate i-cache of any FLASH data */
301 /* invalidate existing TLB entry for flash */
302 disable_tlb(flash_esel);
304 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
305 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */
306 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
310 int board_eth_init(bd_t *bis)
312 struct fsl_pq_mdio_info mdio_info;
313 struct tsec_info_struct tsec_info[4];
314 ccsr_gur_t *gur __attribute__((unused)) =
315 (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
317 #ifdef CONFIG_VSC7385_ENET
319 unsigned int vscfw_addr;
323 SET_STD_TSEC_INFO(tsec_info[num], 1);
327 SET_STD_TSEC_INFO(tsec_info[num], 2);
328 if (is_serdes_configured(SGMII_TSEC2)) {
329 printf("eTSEC2 is in sgmii mode.\n");
330 tsec_info[num].flags |= TSEC_SGMII;
335 SET_STD_TSEC_INFO(tsec_info[num], 3);
340 printf("No TSECs initialized\n");
344 #ifdef CONFIG_VSC7385_ENET
345 /* If a VSC7385 microcode image is present, then upload it. */
346 if ((tmp = getenv("vscfw_addr")) != NULL) {
347 vscfw_addr = simple_strtoul(tmp, NULL, 16);
348 printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
349 if (vsc7385_upload_firmware((void *) vscfw_addr,
350 CONFIG_VSC7385_IMAGE_SIZE))
351 puts("Failure uploading VSC7385 microcode.\n");
353 puts("No address specified for VSC7385 microcode.\n");
356 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
357 mdio_info.name = DEFAULT_MII_NAME;
359 fsl_pq_mdio_init(bis, &mdio_info);
361 tsec_eth_init(bis, tsec_info, num);
363 #if defined(CONFIG_UEC_ETH)
364 /* QE0 and QE3 need to be exposed for UCC1 and UCC5 Eth mode */
365 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE0);
366 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE3);
368 uec_standard_init(bis);
371 return pci_eth_init(bis);
374 #if defined(CONFIG_QE) && \
375 (defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB))
376 static void fdt_board_fixup_qe_pins(void *blob)
381 fsl_lbc_t *lbc = LBC_BASE_ADDR;
383 if (hwconfig("qe")) {
384 /* For QE and eLBC pins multiplexing,
385 * there is a PCA9555 device on P1025RDB.
386 * It control the multiplex pins' functions,
387 * and setting the PCA9555 can switch the
388 * function between QE and eLBC.
390 oldbus = i2c_get_bus_num();
393 val8 = PCA_IOPORT_QE_TDM_ENABLE;
395 val8 = PCA_IOPORT_QE_PIN_ENABLE;
396 i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_CFG_CMD,
398 i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_OUTPUT_CMD,
400 i2c_set_bus_num(oldbus);
401 /* if run QE TDM, Set ABSWP to implement
402 * conversion of addresses in the eLBC.
404 if (hwconfig("tdm")) {
405 set_lbc_or(2, CONFIG_PMC_OR_PRELIM);
406 set_lbc_br(2, CONFIG_PMC_BR_PRELIM);
407 setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
410 node = fdt_path_offset(blob, "/qe");
412 fdt_del_node(blob, node);
419 #ifdef CONFIG_OF_BOARD_SETUP
420 void ft_board_setup(void *blob, bd_t *bd)
424 const char *soc_usb_compat = "fsl-usb2-dr";
425 int err, usb1_off, usb2_off;
427 ft_cpu_setup(blob, bd);
429 base = getenv_bootm_low();
430 size = getenv_bootm_size();
432 fdt_fixup_memory(blob, (u64)base, (u64)size);
437 do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
439 #if defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB)
440 fdt_board_fixup_qe_pins(blob);
444 #if defined(CONFIG_HAS_FSL_DR_USB)
445 fdt_fixup_dr_usb(blob, bd);
448 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
449 /* Delete eLBC node as it is muxed with USB2 controller */
450 if (hwconfig("usb2")) {
451 const char *soc_elbc_compat = "fsl,p1020-elbc";
452 int off = fdt_node_offset_by_compatible(blob, -1,
455 printf("WARNING: could not find compatible node %s: %s.\n",
460 err = fdt_del_node(blob, off);
462 printf("WARNING: could not remove %s: %s.\n",
463 soc_elbc_compat, fdt_strerror(err));
469 /* Delete USB2 node as it is muxed with eLBC */
470 usb1_off = fdt_node_offset_by_compatible(blob, -1,
473 printf("WARNING: could not find compatible node %s: %s.\n",
475 fdt_strerror(usb1_off));
478 usb2_off = fdt_node_offset_by_compatible(blob, usb1_off,
481 printf("WARNING: could not find compatible node %s: %s.\n",
483 fdt_strerror(usb2_off));
486 err = fdt_del_node(blob, usb2_off);
488 printf("WARNING: could not remove %s: %s.\n",
489 soc_usb_compat, fdt_strerror(err));