1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
14 #include <asm/processor.h>
16 #include <asm/cache.h>
17 #include <asm/immap_85xx.h>
18 #include <asm/fsl_pci.h>
19 #include <fsl_ddr_sdram.h>
21 #include <asm/fsl_law.h>
22 #include <asm/fsl_lbc.h>
25 #include <linux/libfdt.h>
26 #include <fdt_support.h>
31 #include <asm/fsl_serdes.h>
36 #define GPIO_GETH_SW_PORT 1
37 #define GPIO_GETH_SW_PIN 29
38 #define GPIO_GETH_SW_DATA (1 << (31 - GPIO_GETH_SW_PIN))
40 #define GPIO_SLIC_PORT 1
41 #define GPIO_SLIC_PIN 30
42 #define GPIO_SLIC_DATA (1 << (31 - GPIO_SLIC_PIN))
44 #if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
45 #define GPIO_DDR_RST_PORT 1
46 #define GPIO_DDR_RST_PIN 8
47 #define GPIO_DDR_RST_DATA (1 << (31 - GPIO_DDR_RST_PIN))
49 #define GPIO_2BIT_MASK (0x3 << (32 - (GPIO_DDR_RST_PIN + 1) * 2))
52 #if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB)
53 #define PCA_IOPORT_I2C_ADDR 0x23
54 #define PCA_IOPORT_OUTPUT_CMD 0x2
55 #define PCA_IOPORT_CFG_CMD 0x6
56 #define PCA_IOPORT_QE_PIN_ENABLE 0xf8
57 #define PCA_IOPORT_QE_TDM_ENABLE 0xf6
60 const qe_iop_conf_t qe_iop_conf_tab[] = {
62 {1, 1, 2, 0, 0}, /* GPIO7/PB1 - LOAD_DEFAULT_N */
63 #if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
64 {1, 8, 1, 1, 0}, /* GPIO10/PB8 - DDR_RST */
66 {0, 15, 1, 0, 0}, /* GPIO11/A15 - WDI */
67 {GPIO_GETH_SW_PORT, GPIO_GETH_SW_PIN, 1, 0, 0}, /* RST_GETH_SW_N */
68 {GPIO_SLIC_PORT, GPIO_SLIC_PIN, 1, 0, 0}, /* RST_SLIC_N */
70 #ifdef CONFIG_TARGET_P1025RDB
72 {1, 19, 1, 0, 1}, /* QE_MUX_MDC */
75 {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */
78 {0, 23, 2, 0, 2}, /* CLK12 */
79 {0, 24, 2, 0, 1}, /* CLK9 */
80 {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
81 {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
82 {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
83 {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
84 {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
85 {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
86 {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
87 {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
88 {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
89 {0, 13, 1, 0, 2}, /* ENET1_TX_ER */
90 {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */
91 {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */
92 {0, 17, 2, 0, 2}, /* ENET1_CRS */
93 {0, 16, 2, 0, 2}, /* ENET1_COL */
96 {1, 11, 2, 0, 1}, /* CLK13 */
97 {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
98 {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
99 {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
100 {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
101 {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */
102 {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */
103 {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */
106 {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
119 u8 status_led; /* offset: 0x8 */
120 u8 fxo_led; /* offset: 0x9 */
121 u8 fxs_led; /* offset: 0xa */
123 u8 system_rst; /* offset: 0xd */
129 #define CPLD_WD_CFG 0x03
130 #define CPLD_RST_BSW 0x00
131 #define CPLD_RST_BWD 0x00
132 #define CPLD_BYPASS_EN 0x03
133 #define CPLD_STATUS_LED 0x01
134 #define CPLD_FXO_LED 0x01
135 #define CPLD_FXS_LED 0x0F
136 #define CPLD_SYS_RST 0x00
138 void board_cpld_init(void)
140 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
142 out_8(&cpld_data->wd_cfg, CPLD_WD_CFG);
143 out_8(&cpld_data->status_led, CPLD_STATUS_LED);
144 out_8(&cpld_data->fxo_led, CPLD_FXO_LED);
145 out_8(&cpld_data->fxs_led, CPLD_FXS_LED);
146 out_8(&cpld_data->system_rst, CPLD_SYS_RST);
149 void board_gpio_init(void)
152 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
153 par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
155 #if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
157 setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
159 clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
161 setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
163 clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdir1, GPIO_2BIT_MASK);
165 /* Enable VSC7385 switch */
166 setbits_be32(&par_io[GPIO_GETH_SW_PORT].cpdat, GPIO_GETH_SW_DATA);
169 setbits_be32(&par_io[GPIO_SLIC_PORT].cpdat, GPIO_SLIC_DATA);
172 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
175 * GPIO10 DDR Reset, open drain
176 * GPIO7 LOAD_DEFAULT_N Input
177 * GPIO11 WDI (watchdog input)
178 * GPIO12 Ethernet Switch Reset
182 setbits_be32(&pgpio->gpdir, 0x02130000);
183 #if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL)
184 /* init DDR3 reset signal */
185 setbits_be32(&pgpio->gpdir, 0x00200000);
186 setbits_be32(&pgpio->gpodr, 0x00200000);
187 clrbits_be32(&pgpio->gpdat, 0x00200000);
189 setbits_be32(&pgpio->gpdat, 0x00200000);
191 clrbits_be32(&pgpio->gpdir, 0x00200000);
194 #ifdef CONFIG_VSC7385_ENET
195 /* reset VSC7385 Switch */
196 setbits_be32(&pgpio->gpdir, 0x00080000);
197 setbits_be32(&pgpio->gpdat, 0x00080000);
202 setbits_be32(&pgpio->gpdir, 0x00040000);
203 setbits_be32(&pgpio->gpdat, 0x00040000);
208 int board_early_init_f(void)
210 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
212 setbits_be32(&gur->pmuxcr,
213 (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
214 clrbits_be32(&gur->sdhcdcr, SDHCDCR_CD_INV);
216 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
217 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_ENA);
227 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
228 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
229 u8 in, out, io_config, val;
231 printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n", CONFIG_BOARDNAME,
232 in_8(&cpld_data->cpld_rev_major) & 0x0F,
233 in_8(&cpld_data->cpld_rev_minor) & 0x0F,
234 in_8(&cpld_data->pcba_rev) & 0x0F);
236 /* Initialize i2c early for rom_loc and flash bank information */
237 i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
239 if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
240 i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
241 i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) {
242 printf("Error reading i2c boot information!\n");
243 return 0; /* Don't want to hang() on this error */
246 val = (in & io_config) | (out & (~io_config));
249 if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) {
252 } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SPI) {
255 #ifdef __SW_BOOT_NAND
256 } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_NAND) {
259 #ifdef __SW_BOOT_PCIE
260 } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_PCIE) {
265 puts("nor lower bank");
267 puts("nor upper bank");
272 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
273 puts("SD/MMC : 8-bit Mode\n");
274 puts("eSPI : Disabled\n");
276 puts("SD/MMC : 4-bit Mode\n");
277 puts("eSPI : Enabled\n");
283 #if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
284 void pci_init_board(void)
286 fsl_pcie_init_board(0);
290 int board_early_init_r(void)
292 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
293 int flash_esel = find_tlb_idx((void *)flashbase, 1);
296 * Remap Boot flash region to caching-inhibited
297 * so that flash can be erased properly.
300 /* Flush d-cache and invalidate i-cache of any FLASH data */
304 if (flash_esel == -1) {
305 /* very unlikely unless something is messed up */
306 puts("Error: Could not find TLB for FLASH BASE\n");
307 flash_esel = 2; /* give our best effort to continue */
309 /* invalidate existing TLB entry for flash */
310 disable_tlb(flash_esel);
313 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
314 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */
315 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
319 int board_eth_init(bd_t *bis)
321 struct fsl_pq_mdio_info mdio_info;
322 struct tsec_info_struct tsec_info[4];
323 ccsr_gur_t *gur __attribute__((unused)) =
324 (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
326 #ifdef CONFIG_VSC7385_ENET
328 unsigned int vscfw_addr;
332 SET_STD_TSEC_INFO(tsec_info[num], 1);
336 SET_STD_TSEC_INFO(tsec_info[num], 2);
337 if (is_serdes_configured(SGMII_TSEC2)) {
338 printf("eTSEC2 is in sgmii mode.\n");
339 tsec_info[num].flags |= TSEC_SGMII;
344 SET_STD_TSEC_INFO(tsec_info[num], 3);
349 printf("No TSECs initialized\n");
353 #ifdef CONFIG_VSC7385_ENET
354 /* If a VSC7385 microcode image is present, then upload it. */
355 tmp = env_get("vscfw_addr");
357 vscfw_addr = simple_strtoul(tmp, NULL, 16);
358 printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
359 if (vsc7385_upload_firmware((void *) vscfw_addr,
360 CONFIG_VSC7385_IMAGE_SIZE))
361 puts("Failure uploading VSC7385 microcode.\n");
363 puts("No address specified for VSC7385 microcode.\n");
366 mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1);
367 mdio_info.name = DEFAULT_MII_NAME;
369 fsl_pq_mdio_init(bis, &mdio_info);
371 tsec_eth_init(bis, tsec_info, num);
373 #if defined(CONFIG_UEC_ETH)
374 /* QE0 and QE3 need to be exposed for UCC1 and UCC5 Eth mode */
375 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE0);
376 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE3);
378 uec_standard_init(bis);
381 return pci_eth_init(bis);
384 #if defined(CONFIG_QE) && \
385 (defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB))
386 static void fdt_board_fixup_qe_pins(void *blob)
391 fsl_lbc_t *lbc = LBC_BASE_ADDR;
393 if (hwconfig("qe")) {
394 /* For QE and eLBC pins multiplexing,
395 * there is a PCA9555 device on P1025RDB.
396 * It control the multiplex pins' functions,
397 * and setting the PCA9555 can switch the
398 * function between QE and eLBC.
400 oldbus = i2c_get_bus_num();
403 val8 = PCA_IOPORT_QE_TDM_ENABLE;
405 val8 = PCA_IOPORT_QE_PIN_ENABLE;
406 i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_CFG_CMD,
408 i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_OUTPUT_CMD,
410 i2c_set_bus_num(oldbus);
411 /* if run QE TDM, Set ABSWP to implement
412 * conversion of addresses in the eLBC.
414 if (hwconfig("tdm")) {
415 set_lbc_or(2, CONFIG_PMC_OR_PRELIM);
416 set_lbc_br(2, CONFIG_PMC_BR_PRELIM);
417 setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
420 node = fdt_path_offset(blob, "/qe");
422 fdt_del_node(blob, node);
429 #ifdef CONFIG_OF_BOARD_SETUP
430 int ft_board_setup(void *blob, bd_t *bd)
434 #if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
435 const char *soc_usb_compat = "fsl-usb2-dr";
436 int usb_err, usb1_off, usb2_off;
438 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
442 ft_cpu_setup(blob, bd);
444 base = env_get_bootm_low();
445 size = env_get_bootm_size();
447 fdt_fixup_memory(blob, (u64)base, (u64)size);
449 #if !defined(CONFIG_DM_PCI)
454 do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
456 #if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB)
457 fdt_board_fixup_qe_pins(blob);
461 #if defined(CONFIG_HAS_FSL_DR_USB)
462 fsl_fdt_fixup_dr_usb(blob, bd);
465 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
466 /* Delete eLBC node as it is muxed with USB2 controller */
467 if (hwconfig("usb2")) {
468 const char *soc_elbc_compat = "fsl,p1020-elbc";
469 int off = fdt_node_offset_by_compatible(blob, -1,
472 printf("WARNING: could not find compatible node %s\n",
476 err = fdt_del_node(blob, off);
478 printf("WARNING: could not remove %s\n",
486 #if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
487 /* Delete USB2 node as it is muxed with eLBC */
488 usb1_off = fdt_node_offset_by_compatible(blob, -1,
491 printf("WARNING: could not find compatible node %s\n",
495 usb2_off = fdt_node_offset_by_compatible(blob, usb1_off,
498 printf("WARNING: could not find compatible node %s\n",
502 usb_err = fdt_del_node(blob, usb2_off);
504 printf("WARNING: could not remove %s\n", soc_usb_compat);