1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
9 #include <asm/immap_85xx.h>
10 #include <asm/processor.h>
11 #include <fsl_ddr_sdram.h>
12 #include <fsl_ddr_dimm_params.h>
14 #include <asm/fsl_law.h>
16 #ifdef CONFIG_SYS_DDR_RAW_TIMING
17 #if defined(CONFIG_P1020RDB_PROTO)
18 /* Micron MT41J256M8_187E */
19 dimm_params_t ddr_raw_timing = {
21 .rank_density = 1073741824u,
22 .capacity = 1073741824u,
23 .primary_sdram_width = 32,
29 .n_banks_per_sdram_device = 8,
31 .burst_lengths_bitmask = 0x0c,
34 .caslat_x = 0x1e << 4, /* 5,6,7,8 */
45 .refresh_rate_ps = 7800000,
48 #elif defined(CONFIG_TARGET_P2020RDB)
49 /* Micron MT41J128M16_15E */
50 dimm_params_t ddr_raw_timing = {
52 .rank_density = 1073741824u,
53 .capacity = 1073741824u,
54 .primary_sdram_width = 64,
60 .n_banks_per_sdram_device = 8,
62 .burst_lengths_bitmask = 0x0c,
65 .caslat_x = 0x7e << 4, /* 5,6,7,8,9,10 */
76 .refresh_rate_ps = 7800000,
79 #elif (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
80 /* Micron MT41J512M8_187E */
81 dimm_params_t ddr_raw_timing = {
83 .rank_density = 1073741824u,
84 .capacity = 2147483648u,
85 .primary_sdram_width = 32,
91 .n_banks_per_sdram_device = 8,
93 .burst_lengths_bitmask = 0x0c,
96 .caslat_x = 0x1e << 4, /* 5,6,7,8 */
107 .refresh_rate_ps = 7800000,
110 #elif defined(CONFIG_TARGET_P1020RDB_PC)
112 * Samsung K4B2G0846C-HCF8
113 * The following timing are for "downshift"
114 * i.e. to use CL9 part as CL7
115 * otherwise, tAA, tRCD, tRP will be 13500ps
116 * and tRC will be 49500ps
118 dimm_params_t ddr_raw_timing = {
120 .rank_density = 1073741824u,
121 .capacity = 1073741824u,
122 .primary_sdram_width = 32,
124 .registered_dimm = 0,
128 .n_banks_per_sdram_device = 8,
130 .burst_lengths_bitmask = 0x0c,
133 .caslat_x = 0x1e << 4, /* 5,6,7,8 */
144 .refresh_rate_ps = 7800000,
147 #elif defined(CONFIG_TARGET_P1024RDB)
149 * Samsung K4B2G0846C-HCH9
150 * The following timing are for "downshift"
151 * i.e. to use CL9 part as CL7
152 * otherwise, tAA, tRCD, tRP will be 13500ps
153 * and tRC will be 49500ps
155 dimm_params_t ddr_raw_timing = {
157 .rank_density = 1073741824u,
158 .capacity = 1073741824u,
159 .primary_sdram_width = 32,
161 .registered_dimm = 0,
165 .n_banks_per_sdram_device = 8,
167 .burst_lengths_bitmask = 0x0c,
170 .caslat_x = 0x3e << 4, /* 5,6,7,8,9 */
181 .refresh_rate_ps = 7800000,
185 #error Missing raw timing data for this board
188 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
189 unsigned int controller_number,
190 unsigned int dimm_number)
192 const char dimm_model[] = "Fixed DDR on board";
194 if ((controller_number == 0) && (dimm_number == 0)) {
195 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
196 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
197 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
202 #endif /* CONFIG_SYS_DDR_RAW_TIMING */
204 #ifdef CFG_SYS_DDR_CS0_BNDS
205 /* Fixed sdram init -- doesn't use serial presence detect. */
206 phys_size_t fixed_sdram(void)
211 fsl_ddr_cfg_regs_t ddr_cfg_regs = {
212 .cs[0].bnds = CFG_SYS_DDR_CS0_BNDS,
213 .cs[0].config = CFG_SYS_DDR_CS0_CONFIG,
214 .cs[0].config_2 = CFG_SYS_DDR_CS0_CONFIG_2,
215 #if CONFIG_CHIP_SELECTS_PER_CTRL > 1
216 .cs[1].bnds = CFG_SYS_DDR_CS1_BNDS,
217 .cs[1].config = CFG_SYS_DDR_CS1_CONFIG,
218 .cs[1].config_2 = CFG_SYS_DDR_CS1_CONFIG_2,
220 .timing_cfg_3 = CFG_SYS_DDR_TIMING_3,
221 .timing_cfg_0 = CFG_SYS_DDR_TIMING_0,
222 .timing_cfg_1 = CFG_SYS_DDR_TIMING_1,
223 .timing_cfg_2 = CFG_SYS_DDR_TIMING_2,
224 .ddr_sdram_cfg = CFG_SYS_DDR_CONTROL,
225 .ddr_sdram_cfg_2 = CFG_SYS_DDR_CONTROL_2,
226 .ddr_sdram_mode = CFG_SYS_DDR_MODE_1,
227 .ddr_sdram_mode_2 = CFG_SYS_DDR_MODE_2,
228 .ddr_sdram_md_cntl = CFG_SYS_DDR_MODE_CONTROL,
229 .ddr_sdram_interval = CFG_SYS_DDR_INTERVAL,
230 .ddr_data_init = 0xdeadbeef, /* Poison value */
231 .ddr_sdram_clk_cntl = CFG_SYS_DDR_CLK_CTRL,
232 .ddr_init_addr = CFG_SYS_DDR_INIT_ADDR,
233 .ddr_init_ext_addr = CFG_SYS_DDR_INIT_EXT_ADDR,
234 .timing_cfg_4 = CFG_SYS_DDR_TIMING_4,
235 .timing_cfg_5 = CFG_SYS_DDR_TIMING_5,
236 .ddr_zq_cntl = CFG_SYS_DDR_ZQ_CONTROL,
237 .ddr_wrlvl_cntl = CFG_SYS_DDR_WRLVL_CONTROL,
238 .ddr_sr_cntr = CFG_SYS_DDR_SR_CNTR,
239 .ddr_sdram_rcw_1 = CFG_SYS_DDR_RCW_1,
240 .ddr_sdram_rcw_2 = CFG_SYS_DDR_RCW_2
243 get_sys_info(&sysinfo);
244 printf("Configuring DDR for %s MT/s data rate\n",
245 strmhz(buf, sysinfo.freq_ddrbus));
247 ddr_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024;
249 fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
251 if (set_ddr_laws(CFG_SYS_DDR_SDRAM_BASE,
252 ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
253 printf("ERROR setting Local Access Windows for DDR\n");
261 void fsl_ddr_board_options(memctl_options_t *popts,
262 dimm_params_t *pdimm,
263 unsigned int ctrl_num)
266 popts->clk_adjust = 6;
267 popts->cpo_override = 0x1f;
268 popts->write_data_delay = 2;
269 popts->half_strength_driver_enable = 1;
270 /* Write leveling override */
272 popts->wrlvl_override = 1;
273 popts->wrlvl_sample = 0xf;
274 popts->wrlvl_start = 0x8;
275 popts->trwt_override = 1;
278 if (pdimm->primary_sdram_width == 64)
279 popts->data_bus_width = 0;
280 else if (pdimm->primary_sdram_width == 32)
281 popts->data_bus_width = 1;
283 printf("Error in DDR bus width configuration!\n");
285 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
286 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
287 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;